diff -Nrcpad gcc-16-20260606/LAST_UPDATED gcc-16-20260613/LAST_UPDATED
*** gcc-16-20260606/LAST_UPDATED	Sat Jun  6 22:32:21 2026
--- gcc-16-20260613/LAST_UPDATED	Sat Jun 13 22:32:20 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-16 revision 3b762dc6f04bf0f8613d7065267c6f2759330a61
--- 1 ----
! Obtained from git: releases/gcc-16 revision 7a86e74e62b6d1f2013673f623ec4e7c257d5035
diff -Nrcpad gcc-16-20260606/MD5SUMS gcc-16-20260613/MD5SUMS
*** gcc-16-20260606/MD5SUMS	Sat Jun  6 22:32:26 2026
--- gcc-16-20260613/MD5SUMS	Sat Jun 13 22:32:25 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260606.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260613.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
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*** 580,586 ****
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*** 2207,2213 ****
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*************** ea821c9d267c64dd8b74aad9d0189834  gcc/c-
*** 3333,3339 ****
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--- 3333,3339 ----
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*************** cbfdd140f14c43c01a6bdf8b1c24b317  gcc/c/
*** 3344,3350 ****
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--- 3344,3350 ----
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*************** b218f741c2f54f950d065bb40f5125ea  gcc/co
*** 3466,3474 ****
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--- 3466,3474 ----
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*************** d3b8ce30c6110489fd0b57d6792f3f29  gcc/co
*** 3504,3510 ****
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--- 3504,3510 ----
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*************** b05978bd2969a943265d3549c23b8b59  gcc/co
*** 3875,3881 ****
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--- 3875,3881 ----
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*************** c40c01da4802f0f9431628ebe3d73752  gcc/co
*** 4226,4231 ****
--- 4226,4233 ----
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*************** dbcdd5d37809de3b588c89731b456a95  gcc/co
*** 4235,4241 ****
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--- 4237,4243 ----
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*************** ca79ed6b45db789c76673ad8ab56752f  gcc/co
*** 4253,4259 ****
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--- 4255,4261 ----
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*************** b18770c338209a9276ef5d52a49bde7b  gcc/co
*** 4285,4291 ****
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--- 4287,4293 ----
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*************** dca59d9c03f5b12366f9a926169f396d  gcc/co
*** 4296,4302 ****
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--- 4298,4304 ----
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*************** b63569ecff9557acb7963f14a101bce1  gcc/co
*** 4304,4312 ****
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*************** bc129bffab46f1b3f4e8385e129dad2d  gcc/co
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*************** db114ac74c87743a142214fddaad2687  gcc/co
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*************** b4cde95b709fc93c90bf4d6b3edc7fd0  gcc/co
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*************** bdb78e19d53ecbecb7fa47ce6ea09c60  gcc/co
*** 4751,4757 ****
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*************** c5ad0142a191862e3e81ecd3573754b3  gcc/co
*** 5644,5650 ****
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*************** b9032a113a137533247a90fda508e897  gcc/cp
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*************** b98d31c57aa038618db60991b17e0d35  gcc/cp
*** 5734,5740 ****
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*************** ee65c9e3e7c3fb1fd0128c23f4130e51  gcc/do
*** 6129,6135 ****
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*************** f80b38c70a85f9aeae9688b937b028ba  gcc/fi
*** 6269,6275 ****
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*************** edad5176d72953374d67effefef0a605  gcc/fo
*** 6311,6317 ****
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--- 6313,6319 ----
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*************** a0c40b654df0b5c5213047d26e48e97a  gcc/fo
*** 6364,6370 ****
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--- 6366,6372 ----
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*************** f24751f278bee1ac8dc861467d9f96a3  gcc/ta
*** 8724,8730 ****
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*** 35065,35071 ****
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*** 37803,37808 ****
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*** 37901,37906 ****
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*** 83165,83170 ****
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*** 117119,117124 ****
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  761826027ebb1cfbb089d23904494606  libgcc/config/avr/libf7/t-libf7-math-symbols
  2203329f7323549e6c781eca3437d2e0  libgcc/config/avr/t-avr
*************** a73d560a3ba317c5ad0a7919d87b4b6d  libssp
*** 145875,145881 ****
  7d75fa0d30318408fe4cd91d9cbe3ac7  libssp/vsnprintf-chk.c
  e9ff0f4bdd1be75a507480ed1267459d  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! f519f1cdc6e815671f8a7680406880a5  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 145890,145896 ----
  7d75fa0d30318408fe4cd91d9cbe3ac7  libssp/vsnprintf-chk.c
  e9ff0f4bdd1be75a507480ed1267459d  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! cceca80a403fd87523ee81b78bad149d  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
diff -Nrcpad gcc-16-20260606/gcc/ChangeLog gcc-16-20260613/gcc/ChangeLog
*** gcc-16-20260606/gcc/ChangeLog	Sat Jun  6 22:32:04 2026
--- gcc-16-20260613/gcc/ChangeLog	Sat Jun 13 22:32:05 2026
***************
*** 1,3 ****
--- 1,633 ----
+ 2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125751
+ 	* config/avr/avr.cc (avr_out_fract): Fix too small sequence
+ 	lengths in avr_asm_len calls.
+ 
+ 2026-06-11  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	PR testsuite/113276
+ 	* doc/sourcebuild.texi (arm_mixed_fp): Document.
+ 
+ 2026-06-09  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-06-08  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* config/mips/sync.md (sync_old_<optab><mode>): Fix
+ 	uninitialized operand use.
+ 	(sync_new_<optab><mode>): Fix uninitialized operand use, use the
+ 	same expression for the set source of operand 0 and 1.
+ 
+ 2026-06-09  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-05-28  Kewen Lin  <linkewen@hygon.cn>
+ 		    Xin Liu  <liulxx@hygon.cn>
+ 
+ 	* config/i386/c86-4g-m7.md (c86_4g_m7_fpu): Remove automaton.
+ 	(c86_4g_m7_fpu02): New automaton.
+ 	(c86_4g_m7_fpu13): Ditto.
+ 	(c86-4g-m7-fpu0): Move to c86_4g_m7_fpu02 automaton.
+ 	(c86-4g-m7-fpu1): Move to c86_4g_m7_fpu13 automaton.
+ 	(c86-4g-m7-fpu2): Move to c86_4g_m7_fpu02 automaton.
+ 	(c86-4g-m7-fpu3): Move to c86_4g_m7_fpu13 automaton.
+ 	(c86-4g-m7-fdiv): Remove cpu unit.
+ 	(c86-4g-m7-fdiv1): New cpu unit.
+ 	(c86-4g-m7-fdiv3): Ditto.
+ 	(c86-4g-m7-fpu_0_3): New reservation.
+ 	(c86-4g-m7-fpu_1_3x2): Ditto.
+ 	(c86-4g-m7-fpu_1_3x3): Ditto.
+ 	(c86-4g-m7-fpu_1_3x6): Ditto.
+ 	(c86-4g-m7-fpux2): Ditto.
+ 	(c86-4g-m7-fpux4): Ditto.
+ 	(c86-4g-m7-fpux6): Ditto.
+ 	(c86-4g-m7-fpux8): Ditto.
+ 	(c86-4g-m7-fpux16): Ditto.
+ 	(c86-4g-m7-fp1fdiv1x4): Ditto.
+ 	(c86-4g-m7-fp3fdiv3x4): Ditto.
+ 	(c86-4g-m7-fdiv13): Ditto.
+ 	(c86-4g-m7-fp13div13): Ditto.
+ 	(c86-4g-m7-fp13div13x4): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x8): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x9): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x11): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x15): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x18): Ditto.
+ 	(c86_4g_m7_idiv): New reservation.
+ 	(c86_4g_m7_idiv_QI): Adjust reservation latency and unit occupancy.
+ 	(c86_4g_m7_idiv_load): New reservation.
+ 	(c86_4g_m7_idiv_QI_load): Adjust reservation latency and unit
+ 	occupancy.
+ 	(c86_4g_m7_idiv_DI): Remove reservation.
+ 	(c86_4g_m7_idiv_SI): Ditto.
+ 	(c86_4g_m7_idiv_HI): Ditto.
+ 	(c86_4g_m7_idiv_DI_load): Ditto.
+ 	(c86_4g_m7_idiv_SI_load): Ditto.
+ 	(c86_4g_m7_idiv_HI_load): Ditto.
+ 	(c86_4g_m7_sse_insertimm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_insert): Ditto.
+ 	(c86_4g_m7_fp_sqrt): Adjust reservation.
+ 	(c86_4g_m7_fp_div): Ditto.
+ 	(c86_4g_m7_fp_div_load): Ditto.
+ 	(c86_4g_m7_fp_idiv_load): Ditto.
+ 	(c86_4g_m7_sse_pinsr_reg): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_pinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_xmm): Delete the prefix condition.
+ 	(c86_4g_m7_avx512_perm_xmm_opload): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_permi2_zmm): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm_load): Ditto.
+ 	(c86_4g_m7_avx512_permi2_zmm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_noimm): Ditto.
+ 	(c86_4g_m7_sse_perm_zmm_noimm_load): Ditto.
+ 	(c86_4g_m7_avx_perm_ymm): Remove.
+ 	(c86_4g_m7_avx_perm_ymem): Ditto.
+ 	(c86_4g_m7_avx512_shuf_zmm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_shuf_zmem): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr_load): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi_load): Ditto.
+ 	(c86_4g_m7_avx512_expand): Ditto.
+ 	(c86_4g_m7_avx512_expand_load): Ditto.
+ 	(c86_4g_m7_avx512_expand_z): Ditto.
+ 	(c86_4g_m7_avx512_expand_z_load): Ditto.
+ 	(c86_4g_m7_sse_movnt_xy): Rename to c86_4g_m7_sse_movnt.
+ 	(c86_4g_m7_avx512_sseadd_xy): Adjust reservation units.
+ 	(c86_4g_m7_avx512_sseadd_xy_load): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_hplus): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_sseiadd_hplus_load): Ditto.
+ 	(c86_4g_m7_avx512_ssemul): Adjust reservation units.
+ 	(c86_4g_m7_avx512_ssemul_load): Ditto.
+ 	(c86_4g_m7_avx512_ssediv): Remove.
+ 	(c86_4g_m7_avx512_ssediv_mem): Remove.
+ 	(c86_4g_m7_avx512_ssediv_x): New.
+ 	(c86_4g_m7_avx512_ssediv_xmem): New.
+ 	(c86_4g_m7_avx512_ssediv_y): New.
+ 	(c86_4g_m7_avx512_ssediv_ymem): New.
+ 	(c86_4g_m7_avx512_ssediv_z): Adjust reservation units.
+ 	(c86_4g_m7_avx512_ssediv_zmem): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_z): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_ssecmp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z): New reservation.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_test_z): Remove reservation.
+ 	(c86_4g_m7_avx512_ssecmp_test_z_load): Ditto.
+ 	(c86_4g_m7_avx512_muladd): Broaden matching condition.
+ 	(c86_4g_m7_avx512_muladd_load): Ditto.
+ 	(c86_4g_m7_fma_muladd): Remove reservation.
+ 	(c86_4g_m7_fma_muladd_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_x): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_sse_conflict_x_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_class_z): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_sse_class_z_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt): Remove.
+ 	(c86_4g_m7_avx512_sse_sqrt_load): Remove.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_x): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_xload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_y): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_yload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_z): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_zload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_x): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_xload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_y): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_yload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_z): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_zload): New.
+ 	(c86_4g_m7_avx512_msklog_vector): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_mskmov_z_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_reg): Ditto.
+ 	* config/i386/c86-4g.md (c86_4g_fp): Remove automaton.
+ 	(c86_4g_fp024): New automaton.
+ 	(c86_4g_fp1): Ditto.
+ 	(c86-4g-fp0): Move to c86_4g_fp024 automaton.
+ 	(c86-4g-fp1): Move to c86_4g_fp1 automaton.
+ 	(c86-4g-fp2): Move to c86_4g_fp024 automaton.
+ 	(c86-4g-fp3): Ditto.
+ 	(c86-4g-fp1fdivx4): New reservation.
+ 	(c86_4g_fp_sqrt): Adjust reservation.
+ 	(c86_4g_sse_sqrt_sf): Ditto.
+ 	(c86_4g_sse_sqrt_sf_mem): Ditto.
+ 	(c86_4g_sse_sqrt_df): Ditto.
+ 	(c86_4g_sse_sqrt_df_mem): Ditto.
+ 	(c86_4g_fp_op_div): Ditto.
+ 	(c86_4g_fp_op_div_load): Ditto.
+ 	(c86_4g_fp_op_idiv_load): Adjust reservation latency.
+ 	(c86_4g_ssediv_ss_ps): Adjust reservation.
+ 	(c86_4g_ssediv_ss_ps_load): Ditto.
+ 	(c86_4g_ssediv_sd_pd): Ditto.
+ 	(c86_4g_ssediv_sd_pd_load): Ditto.
+ 	(c86_4g_ssediv_avx256_ps): Ditto.
+ 	(c86_4g_ssediv_avx256_ps_load): Ditto.
+ 	(c86_4g_ssediv_avx256_pd): Ditto.
+ 	(c86_4g_ssediv_avx256_pd_load): Ditto.
+ 
+ 2026-06-09  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-05-01  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	* config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.
+ 	(c86_4g_m7_fdiv): Ditto.
+ 	(c86-4g-m7-idiv): New unit.
+ 	(c86-4g-m7-fdiv): Ditto.
+ 	(c86_4g_m7_idiv_DI): Adjust unit in the reservation.
+ 	(c86_4g_m7_idiv_SI): Ditto.
+ 	(c86_4g_m7_idiv_HI): Ditto.
+ 	(c86_4g_m7_idiv_QI): Ditto.
+ 	(c86_4g_m7_idiv_DI_load): Ditto.
+ 	(c86_4g_m7_idiv_SI_load): Ditto.
+ 	(c86_4g_m7_idiv_HI_load): Ditto.
+ 	(c86_4g_m7_idiv_QI_load): Ditto.
+ 	(c86_4g_m7_fp_div): Ditto.
+ 	(c86_4g_m7_fp_div_load): Ditto.
+ 	(c86_4g_m7_fp_idiv_load): Ditto.
+ 	(c86_4g_m7_avx512_ssediv): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_mem): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_z): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_zmem): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_load): Ditto.
+ 	(c86_4g_m7_fp_sqrt): Ditto.  Rename from ...
+ 	(c86_4g_m7fp_sqrt): ... here.
+ 	* config/i386/c86-4g.md (c86_4g_idiv): New automaton.
+ 	(c86_4g_fdiv): Ditto.
+ 	(c86-4g-idiv): New unit.
+ 	(c86-4g-fdiv): Ditto.
+ 	(c86_4g_idiv_DI): Ditto.
+ 	(c86_4g_idiv_SI): Ditto.
+ 	(c86_4g_idiv_HI): Ditto.
+ 	(c86_4g_idiv_QI): Ditto.
+ 	(c86_4g_idiv_mem_DI): Ditto.
+ 	(c86_4g_idiv_mem_SI): Ditto.
+ 	(c86_4g_idiv_mem_HI): Ditto.
+ 	(c86_4g_idiv_mem_QI): Ditto.
+ 	(c86_4g_fp_sqrt): Ditto.
+ 	(c86_4g_sse_sqrt_sf): Ditto.
+ 	(c86_4g_sse_sqrt_sf_mem): Ditto.
+ 	(c86_4g_sse_sqrt_df): Ditto.
+ 	(c86_4g_sse_sqrt_df_mem): Ditto.
+ 	(c86_4g_fp_op_div): Ditto.
+ 	(c86_4g_fp_op_div_load): Ditto.
+ 	(c86_4g_fp_op_idiv_load): Ditto.
+ 	(c86_4g_ssediv_ss_ps): Ditto.
+ 	(c86_4g_ssediv_ss_ps_load): Ditto.
+ 	(c86_4g_ssediv_ss_pd): Ditto.
+ 	(c86_4g_ssediv_ss_pd_load): Ditto.
+ 	(c86_4g_ssediv_avx256_ps): Ditto.
+ 	(c86_4g_ssediv_avx256_ps_load): Ditto.
+ 	(c86_4g_ssediv_avx256_pd): Ditto.
+ 	(c86_4g_ssediv_avx256_pd_load): Ditto.
+ 
+ 2026-06-09  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-04-29  Xin Liu  <liulxx@hygon.cn>
+ 		    Zhaoling Bao  <baozhaoling@hygon.cn>
+ 
+ 	* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect the specific
+ 	type of HYGON CPU and return HYGON CPU name.
+ 	(cpu_indicator_init): Handle HYGON CPU.
+ 	* common/config/i386/i386-common.cc (processor_names): Add HYGON
+ 	C86-4G processors c86-4g-m{4,6,7}.
+ 	(processor_alias_table): Add hygon, hygonfam18h and c86-4g-m{4,6,7}
+ 	entries.
+ 	(ARRAY_SIZE): Update as new entries added.
+ 	* common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add
+ 	VENDOR_HYGON.
+ 	(enum processor_types): Add HYGONFAM18H.
+ 	(enum processor_subtypes): Add HYGONFAM18H_C86_4G_M{4,6,7}.
+ 	* config.gcc: Add support for c86_4g_m{4,6,7}.
+ 	* config/i386/cpuid.h (signature_HYGON_ebx):  Add signature for HYGON.
+ 	(signature_HYGON_ecx): Ditto.
+ 	(signature_HYGON_edx): Ditto.
+ 	* config/i386/driver-i386.cc (host_detect_local_cpu): Support HYGON
+ 	c86-4g-m4{4,6,7} processors.
+ 	* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
+ 	* config/i386/i386-options.cc (m_C86_4G_M4): New definition.
+ 	(m_C86_4G_M6): Ditto.
+ 	(m_C86_4G_M7): Ditto.
+ 	(m_C86_4G): Ditto.
+ 	(processor_cost_table): Add cost entries for c86-4g-m4{4,6,7}.
+ 	* config/i386/i386.cc (ix86_reassociation_width): Add handlings for
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	* config/i386/i386.h (enum processor_type): Define
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	(PTA_C86_4G_M4): New define.
+ 	(PTA_C86_4G_M6): Ditto.
+ 	(PTA_C86_4G_M7): Ditto.
+ 	* config/i386/x86-tune-costs.h (c86_4g_m4_memcpy): New stringop_algs.
+ 	(c86_4g_m4_cost): New processor_costs.
+ 	(c86_4g_m6_cost): Ditto.
+ 	(c86_4g_m7_cost): Ditto.
+ 	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	(ix86_adjust_cost): Ditto.
+ 	* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Handle m_C86_4G.
+ 	(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
+ 	(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
+ 	(X86_TUNE_USE_LEAVE): Ditto.
+ 	(X86_TUNE_PUSH_MEMORY): Ditto.
+ 	(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
+ 	(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
+ 	(X86_TUNE_USE_SAHF): Ditto.
+ 	(X86_TUNE_USE_BT): Ditto.
+ 	(X86_TUNE_AVOID_MFENCE): Ditto.
+ 	(X86_TUNE_USE_FFREEP): Ditto.
+ 	(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
+ 	(X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL): Ditto.
+ 	(X86_TUNE_SSE_TYPELESS_STORES): Ditto.
+ 	(X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
+ 	(X86_TUNE_USE_GATHER_2PARTS): Ditto.
+ 	(X86_TUNE_USE_GATHER_4PARTS): Ditto.
+ 	(X86_TUNE_USE_GATHER_8PARTS): Ditto.
+ 	(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
+ 	(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.
+ 	(X86_TUNE_USE_RCR): Ditto.
+ 	(X86_TUNE_AVX256_MOVE_BY_PIECES): Handle m_C86_4G_M{4,6}.
+ 	(X86_TUNE_USE_SCATTER_2PARTS): Handle m_C86_4G_M7.
+ 	(X86_TUNE_USE_SCATTER_4PARTS): Ditto.
+ 	(X86_TUNE_USE_SCATTER_8PARTS): Ditto.
+ 	(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Ditto.
+ 	(X86_TUNE_AVX512_SPLIT_REGS): Ditto.
+ 	(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.
+ 	(X86_TUNE_AVX512_MASKED_EPILOGUES): Ditto.
+ 	* doc/extend.texi: Document about hygonfam18h and c86-4g-m{4,6,7}.
+ 	* doc/invoke.texi: Document about c86-4g-m{4,6,7}.
+ 	* config/i386/c86-4g-m7.md: New file for c86-4g-m7 scheduling model
+ 	information.
+ 	* config/i386/c86-4g.md: New file for c86-4g-m{4,6} scheduling model
+ 	information.
+ 	* config/i386/i386.md (cpu attr): Add c86_4g_m{4,6,7}.
+ 	(c86-4g.md): New include.
+ 	(c86-4g-m7.md): Ditto.
+ 	(*cmpi<unord>xf_i387): Set attr c86_decode.
+ 	(*cmpi<unord><MODEF:mode>): Ditto.
+ 	(swap<mode>): Ditto.
+ 	(*swap<mode>): Ditto.
+ 	(extendhisi2): Ditto.
+ 	(floathi<mode>2): Ditto.
+ 	(float<SWI48x:mode>xf2): Ditto.
+ 	(*float<SWI48:mode><MODEF:mode>2): Ditto.
+ 	(*floatdi<MODEF:mode>2_i387): Ditto.
+ 	(*anddi_1_bt): Ditto.
+ 	(*iordi_1_bts): Ditto.
+ 	(*xordi_1_btc): Ditto.
+ 	(*<btsc><mode>): Ditto.
+ 	(*btr<mode>): Ditto.
+ 	(*btsq_imm): Ditto.
+ 	(*btrq_imm): Ditto.
+ 	(*btcq_imm): Ditto.
+ 	(*tzcnt<mode>_1): Ditto.
+ 	(*tzcnt<mode>_1_falsedep): Ditto.
+ 	(*bsf<mode>_1): Ditto.
+ 	(*ctz<mode>2_falsedep): Ditto.
+ 	(*ctzsi2_zext): Ditto.
+ 	(*ctzsi2_zext_falsedep): Ditto.
+ 	(bsr_rex64): Ditto.
+ 	(bsr_rex64_1): Ditto.
+ 	(bsr_rex64_1_zext): Ditto.
+ 	(bsr): Ditto.
+ 	(bsr_1): Ditto.
+ 	(bsr_zext_1): Ditto.
+ 	(*bswaphi2_movbe): Ditto.
+ 	(*bswaphi2): Ditto.
+ 	(bswaphisi2_lowpart): Ditto.
+ 	(fpremxf4_i387): Ditto.
+ 	(fprem1xf4_i387): Ditto.
+ 	(<sincos>xf2): Ditto.
+ 	(sincosxf3): Ditto.
+ 	(fptanxf4_i387): Ditto.
+ 	(atan2xf3): Ditto.
+ 	(fyl2xxf3_i387): Ditto.
+ 	(fyl2xp1xf3_i387): Ditto.
+ 	(fxtractxf3_i387): Ditto.
+ 	(*f2xm1xf2_i387): Ditto.
+ 	(fscalexf4_i387): Ditto.
+ 	(rintxf2): Ditto.
+ 	(*movxi_internal_avx512f): Set attr c86_attr.
+ 	(*movoi_internal_avx): Ditto.
+ 	(*movti_internal): Ditto.
+ 	(*movdi_internal): Ditto.
+ 	(*movsi_internal): Ditto.
+ 	(*movhi_internal): Ditto.
+ 	(*movtf_internal): Ditto.
+ 	(*movdf_internal): Ditto.
+ 	(*movsf_internal): Ditto.
+ 	(*zero_extendsidi2): Ditto.
+ 	(sqrtxf2): Ditto.
+ 	(<smaxmin:code><mode>3): Ditto.
+ 	(*ieee_s<ieee_maxmin><mode>3): Ditto.
+ 	* config/i386/mmx.md (*mmx_maskmovq): Set attr c86_decode.
+ 	(*mmx_maskmovq): Ditto.
+ 	(sse_movntq): Set attr c86_attr.
+ 	(*mmx_blendps): Ditto.
+ 	(mmx_blendvps): Ditto.
+ 	(*mmx_pmaddwd): Ditto.
+ 	(mmx_pblendvb_v8qi): Ditto.
+ 	(mmx_pblendvb_<mode>): Ditto.
+ 	(sse4_1_<code>v4qiv4hi2): Ditto.
+ 	(sse4_1_<code>v2hiv2si2): Ditto.
+ 	(sse4_1_<code>v2qiv2si2): Ditto.
+ 	(sse4_1_<code>v2qiv2hi2): Ditto.
+ 	(*mmx_pinsrd): Ditto.
+ 	(*mmx_pinsrw): Ditto.
+ 	(*mmx_pinsrb): Ditto.
+ 	(*mmx_pextrw): Ditto.
+ 	(*mmx_pextrw<mode>): Ditto.
+ 	(*mmx_pextrw_zext): Ditto.
+ 	(*mmx_pextrb): Ditto.
+ 	(*mmx_pextrb_zext): Ditto.
+ 	(*mmx_pblendw64): Ditto.
+ 	(*mmx_pblendw32): Ditto.
+ 	(*vec_extractv2si_1): Ditto.
+ 	(*vec_extractv2si_1_zext): Ditto.
+ 	(*pinsrw): Ditto.
+ 	(*pinsrb): Ditto.
+ 	(*pextrw): Ditto.
+ 	(*pextrw<mode>): Ditto.
+ 	(*pextrw_zext): Ditto.
+ 	(*pextrb): Ditto.
+ 	(*pextrb_zext): Ditto.
+ 	(*mmx_psadbw): Ditto.
+ 	* config/i386/sse.md (ktest<mode>): Set attr c86_decode.
+ 	(*kortest<mode>): Ditto.
+ 	(sse_cvtsi2ss<rex64namesuffix><round_name>): Ditto.
+ 	(sse2_cvtsi2sd): Ditto.
+ 	(sse2_maskmovdqu): Ditto.
+ 	(*<sse>_dp<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(*<sse4_1_avx2>_mpsadbw): Ditto.
+ 	(pclmulqdq): Ditto.
+ 	(<mask_codefor>conflict<mode><mask_name>): Ditto.
+ 	(<avx512>_blendm<mode>): Set attr c86_attr.
+ 	(sse2_movnti<mode>): Ditto.
+ 	(<sse>_movnt<mode>): Ditto.
+ 	(<sse2>_movnt<mode>): Ditto.
+ 	(<sse>_rcp<mode>2): Ditto.
+ 	(sse_vmrcpv4sf2): Ditto.
+ 	(<mask_codefor>rcp14<mode><mask_name>): Ditto.
+ 	(srcp14<mode>): Ditto.
+ 	(srcp14<mode>_mask): Ditto.
+ 	(<sse>_sqrt<mode>2<mask_name><round_name>): Ditto.
+ 	(<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
+ 	(*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
+ 	(<mask_codefor>rsqrt14<mode><mask_name>): Ditto.
+ 	(rsqrt14<mode>): Ditto.
+ 	(rsqrt14_<mode>_mask"): Ditto.
+ 	(*<code><mode>3<mask_name><round_saeonly_name>): Ditto.
+ 	(ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>): Ditto.
+ 	(*<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name>):
+ 	Ditto.
+ 	(<sse>_ieee_vm<ieee_maxmin><mode>3<mask_scalar_name>
+ 	<round_saeonly_scalar_name>): Ditto.
+ 	(*ieee_<ieee_maxmin><mode>3): Ditto.
+ 	(avx_h<insn>v4df3): Ditto.
+ 	(*sse3_haddv2df3): Ditto.
+ 	(sse3_hsubv2df3): Ditto.
+ 	(*sse3_haddv2df3_low): Ditto.
+ 	(*sse3_hsubv2df3_low): Ditto.
+ 	(avx_h<insn>v8sf3): Ditto.
+ 	(sse3_h<insn>v4sf3): Ditto.
+ 	(*<mask_codefor>reducep<mode><mask_name><round_saeonly_name>): Ditto.
+ 	(reduces<mode><mask_scalar_name><round_saeonly_scalar_name>): Ditto.
+ 	(*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto.
+ 	(<sse>_andnot<mode>3<mask_name>): Ditto.
+ 	(*<code><mode>3<mask_name>): Ditto.
+ 	(*andnot<mode>3): Ditto.
+ 	(<code><mode>3): Ditto.
+ 	(*<code>tf3): Ditto.
+ 	(vec_set<mode>_0): Ditto.
+ 	(@vec_set<mode>_0): Ditto.
+ 	(*sse4_1_extractps): Ditto.
+ 	(vec_extract<mode>): Ditto.
+ 	(<mask_codefor><avx512>_align<mode><mask_name>): Ditto.
+ 	(avx512bw_pmaddwd512<mode><mask_name>): Ditto.
+ 	(*avx2_pmaddw): Ditto.
+ 	(*sse2_pmaddwd): Ditto.
+ 	(*avx2_<code><mode>3): Ditto.
+ 	(*avx512f_<code><mode>3<mask_name>): Ditto.
+ 	(*avx512bw_<code><mode>3<mask_name>): Ditto.
+ 	(*sse4_1_<code><mode>3<mask_name>): Ditto.
+ 	(*<code>v8hi3): Ditto.
+ 	(*<code>v16qi3): Ditto.
+ 	(*andnot<mode>3_mask): Ditto.
+ 	(*<code><mode>3): Ditto.
+ 	(<code>v1ti3): Ditto.
+ 	(<sse2p4_1>_pinsr<ssemodesuffix>): Ditto.
+ 	(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Ditto.
+ 	(<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>
+ 	_1<mask_name>): Ditto.
+ 	(vec_set_lo_<mode><mask_name>): Ditto.
+ 	(vec_set_hi_<mode><mask_name>): Ditto.
+ 	(<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
+ 	(avx512f_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
+ 	(*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1): Ditto.
+ 	(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
+ 	(avx512f_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
+ 	(*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): Ditto.
+ 	(*vec_extract<mode>): Ditto.
+ 	(*vec_extract<PEXTR_MODE12:mode>_zext): Ditto.
+ 	(*vec_extractv16qi_zext): Ditto.
+ 	(*vec_extractv4si): Ditto.
+ 	(*vec_extractv4si_zext): Ditto.
+ 	(*vec_extractv2di_1): Ditto.
+ 	(*vec_concatv2si_sse4_1): Ditto.
+ 	(vec_concatv2di): Ditto.
+ 	(*<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
+ 	(*<sse2_avx2>_psadbw): Ditto.
+ 	(<sse>_movmsk<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Ditto.
+ 	(<sse2_avx2>_pmovmskb): Ditto.
+ 	(*<sse2_avx2>_pmovmskb_zext): Ditto.
+ 	(*sse2_maskmovdqu): Ditto.
+ 	(avx2_ph<plusminus_mnemonic>wv16hi3): Ditto.
+ 	(ssse3_ph<plusminus_mnemonic>wv8hi3): Ditto.
+ 	(ssse3_ph<plusminus_mnemonic>dv4si3): Ditto.
+ 	(avx2_ph<plusminus_mnemonic>dv8si3): Ditto.
+ 	(avx2_pmaddubsw256): Ditto.
+ 	(avx512bw_pmaddubsw512<mode><mask_name>): Ditto.
+ 	(ssse3_pmaddubsw128): Ditto.
+ 	(<ssse3_avx2>_psign<mode>3): Ditto.
+ 	(ssse3_psign<mode>3): Ditto.
+ 	(*abs<mode>2): Ditto.
+ 	(abs<mode>2_mask): Ditto.
+ 	(abs<mode>2_mask): Ditto.
+ 	(sse4a_movnt<mode>): Ditto.
+ 	(sse4a_vmmovnt<mode>): Ditto.
+ 	(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(sse4_1_blendv<ssemodesuffix>): Ditto.
+ 	(<vi8_sse4_1_avx2_avx512>_movntdqa): Ditto.
+ 	(<sse4_1_avx2>_pblendvb): Ditto.
+ 	(sse4_1_pblend<ssemodesuffix>): Ditto.
+ 	(*avx2_pblend<ssemodesuffix>): Ditto.
+ 	(avx2_pblendd<mode>): Ditto.
+ 	(avx2_<code>v16qiv16hi2<mask_name>): Ditto.
+ 	(avx512bw_<code>v32qiv32hi2<mask_name>): Ditto.
+ 	(sse4_1_<code>v8qiv8hi2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Ditto.
+ 	(<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): Ditto.
+ 	(avx2_<code>v8qiv8si2<mask_name>): Ditto.
+ 	(*avx2_<code>v8qiv8si2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v4qiv4si2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v4qiv4si2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v16hiv16si2<mask_name>): Ditto.
+ 	(avx2_<code>v8hiv8si2<mask_name>): Ditto.
+ 	(sse4_1_<code>v4hiv4si2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v4hiv4si2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8qiv8di2<mask_name>): Ditto.
+ 	(*avx512f_<code>v8qiv8di2<mask_name>_1): Ditto.
+ 	(avx2_<code>v4qiv4di2<mask_name>): Ditto.
+ 	(*avx2_<code>v4qiv4di2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v2qiv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2qiv2di2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8hiv8di2<mask_name>): Ditto.
+ 	(avx2_<code>v4hiv4di2<mask_name>): Ditto.
+ 	(*avx2_<code>v4hiv4di2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v2hiv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2hiv2di2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8siv8di2<mask_name>): Ditto.
+ 	(avx2_<code>v4siv4di2<mask_name>): Ditto.
+ 	(sse4_1_<code>v2siv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2siv2di2<mask_name>_1): Ditto.
+ 	(sse4_1_round<ssescalarmodesuffix>): Ditto.
+ 	(*sse4_1_round<ssescalarmodesuffix>"): Ditto.
+ 	(sse4_2_pcmpestri): Ditto.
+ 	(sse4_2_pcmpestrm): Ditto.
+ 	(sse4_2_pcmpestr_cconly): Ditto.
+ 	(sse4_2_pcmpistri): Ditto.
+ 	(sse4_2_pcmpistrm): Ditto.
+ 	(sse4_2_pcmpistr_cconly): Ditto.
+ 	(xop_phadd<u>bw): Ditto.
+ 	(xop_phadd<u>bd): Ditto.
+ 	(xop_phadd<u>bq): Ditto.
+ 	(xop_phadd<u>wd): Ditto.
+ 	(xop_phadd<u>wq): Ditto.
+ 	(xop_phadd<u>dq): Ditto.
+ 	(xop_phsubbw): Ditto.
+ 	(xop_phsubwd): Ditto.
+ 	(xop_phsubdq): Ditto.
+ 	(aesenc): Ditto.
+ 	(aesenclast): Ditto.
+ 	(aesdec): Ditto.
+ 	(aesdeclast): Ditto.
+ 	(aesimc): Ditto.
+ 	(aeskeygenassist): Ditto.
+ 	(<avx2_avx512>_permvar<mode><mask_name>): Ditto.
+ 	(avx2_perm<mode>_1<mask_name>): Ditto.
+ 	(<avx512>_permvar<mode><mask_name>): Ditto.
+ 	(avx512f_perm<mode>_1<mask_name>): Ditto.
+ 	(<mask_codefor>avx512f_broadcast<mode><mask_name>): Ditto.
+ 	(avx_vbroadcastf128_<mode>): Ditto.
+ 	(<mask_codefor>avx512vl_broadcast<mode><mask_name>_1): Ditto.
+ 	(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Ditto.
+ 	(*<avx512>_vpermi2var<mode>3_mask): Ditto.
+ 	(<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto.
+ 	(<avx512>_vpermt2var<mode>3_mask): Ditto.
+ 	(*avx_vperm2f128<mode>_nozero): Ditto.
+ 	(vec_set_lo_<mode><mask_name>): Ditto.
+ 	(vec_set_hi_<mode><mask_name>): Ditto.
+ 	(vec_set_lo_<mode>): Ditto.
+ 	(vec_set_hi_<mode>): Ditto.
+ 	(vec_set_lo_v32qi): Ditto.
+ 	(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(avx_vec_concat<mode>): Ditto.
+ 	(<avx512>_compress<mode>_mask): Ditto.
+ 	(compress<mode>_mask): Ditto.
+ 	(<avx512>_compressstore<mode>_mask): Ditto.
+ 	(compressstore<mode>_mask): Ditto.
+ 	(expand<mode>_mask): Ditto.
+ 	(<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>): Ditto.
+ 	(clz<mode>2<mask_name>): Ditto.
+ 	(vpmadd52<vpmadd52type>v8di): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>_maskz_1): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>_mask): Ditto.
+ 	(vaesdec_<mode>): Ditto.
+ 	(vaesdeclast_<mode>): Ditto.
+ 	(vaesenc_<mode>): Ditto.
+ 	(vaesenclast_<mode>): Ditto.
+ 
+ 2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125611
+ 	* config/i386/sse.md (<ssse3_avx2>_pmulhrsw<mode>3, smulhrs<mode>3):
+ 	Use vector_operand instead of nonimmediate_operand.
+ 
  2026-06-03  Richard Sandiford  <rdsandiford@googlemail.com>
  
  	PR rtl-optimization/125375
diff -Nrcpad gcc-16-20260606/gcc/DATESTAMP gcc-16-20260613/gcc/DATESTAMP
*** gcc-16-20260606/gcc/DATESTAMP	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/DATESTAMP	Sat Jun 13 22:32:05 2026
***************
*** 1 ****
! 20260604
--- 1 ----
! 20260613
diff -Nrcpad gcc-16-20260606/gcc/ada/ChangeLog gcc-16-20260613/gcc/ada/ChangeLog
*** gcc-16-20260606/gcc/ada/ChangeLog	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/ada/ChangeLog	Sat Jun 13 22:32:05 2026
***************
*** 1,3 ****
--- 1,65 ----
+ 2026-06-09  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/125695
+ 	* libgnat/s-genbig.adb ("**"): Do not drop the sign on the floor.
+ 	(Big_Exp): Take into account the parity of the exponent for -2.
+ 
+ 2026-06-06  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* sem_ch3.adb (Analyze_Private_Extension_Declaration): Revert latest
+ 	change.
+ 	(Find_Type_Of_Subtype_Indic): Return Any_Type if Find_Type fails to
+ 	resolve the type.
+ 	* sem_ch12.adb (Analyze_Formal_Derived_Type): Restore more specific
+ 	error recovery path.
+ 
+ 2026-06-06  Ronan Desplanques  <desplanques@adacore.com>
+ 
+ 	* exp_ch6.adb (Needs_BIP_Collection): Fix condition.
+ 
+ 2026-06-06  Mathias Aparicio  <aparicio@adacore.com>
+ 
+ 	* libgnat/a-textio.adb
+ 	(Get_Upper_Half_Char, Get_Upper_Half_Char_Immed): Replace
+ 	Constraint_Error with Data_Error
+ 
+ 2026-06-06  Viljar Indus  <indus@adacore.com>
+ 
+ 	* sem_warn.adb (Warn_On_Suspicious_Index): Only check elements
+ 	that are coming from source.
+ 
+ 2026-06-06  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* sem_ch3.adb (Analyze_Private_Extension_Declaration): Be prepared
+ 	for Find_Type_Of_Subtype_Indic returning no type.
+ 	* sem_ch4.adb (Process_Generic_Instantiation): Give an error if the
+ 	generic instantation is referenced in a generic formal part.
+ 	* sem_ch12.adb (Analyze_Formal_Derived_Type): Return early in every
+ 	case of serious errors.
+ 
+ 2026-06-04  Artur Pietrek  <pietrek@adacore.com>
+ 
+ 	* exp_ch7.adb (Make_Address_For_Finalize): check
+ 	Has_Controlled_Component predicate before emitting the shift to be
+ 	consistant with what Is_Constr_Array_Subt_With_Bounds says.
+ 
+ 2026-06-04  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_ch4.adb (Expand_Allocator_Expression): In the case of access
+ 	discriminants, pass Zero_On_Dynamic_Level to compute the static
+ 	accessibility level of the expression.
+ 	* sem_res.adb (Check_Aliased_Parameter): Pass Zero_On_Dynamic_Level
+ 	to compute the static accessibility level of actual parameters.
+ 
+ 2026-06-04  Piotr Trojanek  <trojanek@adacore.com>
+ 
+ 	* sem_ch9.adb (Analyze_Requeue): Fix unbalanced parens.
+ 
+ 2026-06-04  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* sem_util.ads (In_Reverse_Storage_Order_Object): Adjust.
+ 	* sem_util.adb (In_Reverse_Storage_Order_Object): Rewrite.
+ 
  2026-06-02  Eric Botcazou  <ebotcazou@adacore.com>
  
  	* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Variable>: Validate
diff -Nrcpad gcc-16-20260606/gcc/ada/libgnat/s-genbig.adb gcc-16-20260613/gcc/ada/libgnat/s-genbig.adb
*** gcc-16-20260606/gcc/ada/libgnat/s-genbig.adb	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/ada/libgnat/s-genbig.adb	Sat Jun 13 22:32:06 2026
*************** package body System.Generic_Bignums is
*** 262,268 ****
           --  X ** 1 is X
  
           when 1 =>
!             return Normalize (X.D);
  
           --  X ** 2 is X * X
  
--- 262,268 ----
           --  X ** 1 is X
  
           when 1 =>
!             return Normalize (X.D, X.Neg);
  
           --  X ** 2 is X * X
  
*************** package body System.Generic_Bignums is
*** 331,344 ****
        elsif Y.Len > 1 then
           raise Storage_Error with "exponentiation result is too large";
  
!       --  Special case (+/-)2 ** K, where K is 1 .. 31 using a shift
  
        elsif X.Len = 1 and then X.D (1) = 2 and then Y.D (1) < 32 then
           declare
              D : constant Digit_Vector (1 .. 1) :=
                    [Shift_Left (SD'(1), Natural (Y.D (1)))];
           begin
!             return Normalize (D, X.Neg);
           end;
  
        --  Remaining cases have right operand of one word
--- 331,344 ----
        elsif Y.Len > 1 then
           raise Storage_Error with "exponentiation result is too large";
  
!       --  Special case (+/-)2 ** K, where K is in 1 .. 31, using a left shift
  
        elsif X.Len = 1 and then X.D (1) = 2 and then Y.D (1) < 32 then
           declare
              D : constant Digit_Vector (1 .. 1) :=
                    [Shift_Left (SD'(1), Natural (Y.D (1)))];
           begin
!             return Normalize (D, X.Neg and then (Y.D (1) and 1) = 1);
           end;
  
        --  Remaining cases have right operand of one word
diff -Nrcpad gcc-16-20260606/gcc/c/c-decl.cc gcc-16-20260613/gcc/c/c-decl.cc
*** gcc-16-20260606/gcc/c/c-decl.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/c/c-decl.cc	Sat Jun 13 22:32:06 2026
*************** pushtag (location_t loc, tree name, tree
*** 1709,1715 ****
       NULL-named TYPE_DECL node helps dwarfout.c to know when it needs
       to output a representation of a tagged type, and it also gives
       us a convenient place to record the "scope start" address for the
!      tagged type.  */
  
    TYPE_STUB_DECL (type) = pushdecl (build_decl (loc,
  						TYPE_DECL, NULL_TREE, type));
--- 1709,1716 ----
       NULL-named TYPE_DECL node helps dwarfout.c to know when it needs
       to output a representation of a tagged type, and it also gives
       us a convenient place to record the "scope start" address for the
!      tagged type, and it is used to track whether the type is used
!      in a non-local context via mark_decl_used.  */
  
    TYPE_STUB_DECL (type) = pushdecl (build_decl (loc,
  						TYPE_DECL, NULL_TREE, type));
*************** finish_struct (location_t loc, tree t, t
*** 9970,9975 ****
--- 9971,9993 ----
        warning_at (loc, 0, "union cannot be made transparent");
      }
  
+   tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (t));
+   for (x = TYPE_MAIN_VARIANT (t); x; x = TYPE_NEXT_VARIANT (x))
+     {
+       TYPE_FIELDS (x) = TYPE_FIELDS (t);
+       TYPE_LANG_SPECIFIC (x) = TYPE_LANG_SPECIFIC (t);
+       TYPE_TRANSPARENT_AGGR (x) = TYPE_TRANSPARENT_AGGR (t);
+       TYPE_TYPELESS_STORAGE (x) = TYPE_TYPELESS_STORAGE (t);
+       C_TYPE_FIELDS_READONLY (x) = C_TYPE_FIELDS_READONLY (t);
+       C_TYPE_FIELDS_VOLATILE (x) = C_TYPE_FIELDS_VOLATILE (t);
+       C_TYPE_FIELDS_NON_CONSTEXPR (x) = C_TYPE_FIELDS_NON_CONSTEXPR (t);
+       C_TYPE_FIELDS_HAS_COUNTED_BY (x) = C_TYPE_FIELDS_HAS_COUNTED_BY (t);
+       C_TYPE_VARIABLE_SIZE (x) = C_TYPE_VARIABLE_SIZE (t);
+       C_TYPE_VARIABLY_MODIFIED (x) = C_TYPE_VARIABLY_MODIFIED (t);
+       C_TYPE_INCOMPLETE_VARS (x) = NULL_TREE;
+       TYPE_INCLUDES_FLEXARRAY (x) = TYPE_INCLUDES_FLEXARRAY (t);
+     }
+ 
    /* Check for consistency with previous definition.  */
    if (flag_isoc23 && NULL != enclosing_struct_parse_info)
      {
*************** finish_struct (location_t loc, tree t, t
*** 10024,10046 ****
        c_update_type_canonical (t);
      }
  
-   tree incomplete_vars = C_TYPE_INCOMPLETE_VARS (TYPE_MAIN_VARIANT (t));
-   for (x = TYPE_MAIN_VARIANT (t); x; x = TYPE_NEXT_VARIANT (x))
-     {
-       TYPE_FIELDS (x) = TYPE_FIELDS (t);
-       TYPE_LANG_SPECIFIC (x) = TYPE_LANG_SPECIFIC (t);
-       TYPE_TRANSPARENT_AGGR (x) = TYPE_TRANSPARENT_AGGR (t);
-       TYPE_TYPELESS_STORAGE (x) = TYPE_TYPELESS_STORAGE (t);
-       C_TYPE_FIELDS_READONLY (x) = C_TYPE_FIELDS_READONLY (t);
-       C_TYPE_FIELDS_VOLATILE (x) = C_TYPE_FIELDS_VOLATILE (t);
-       C_TYPE_FIELDS_NON_CONSTEXPR (x) = C_TYPE_FIELDS_NON_CONSTEXPR (t);
-       C_TYPE_FIELDS_HAS_COUNTED_BY (x) = C_TYPE_FIELDS_HAS_COUNTED_BY (t);
-       C_TYPE_VARIABLE_SIZE (x) = C_TYPE_VARIABLE_SIZE (t);
-       C_TYPE_VARIABLY_MODIFIED (x) = C_TYPE_VARIABLY_MODIFIED (t);
-       C_TYPE_INCOMPLETE_VARS (x) = NULL_TREE;
-       TYPE_INCLUDES_FLEXARRAY (x) = TYPE_INCLUDES_FLEXARRAY (t);
-     }
- 
    /* Update type location to the one of the definition, instead of e.g.
       a forward declaration.  */
    if (TYPE_STUB_DECL (t))
--- 10042,10047 ----
*************** declspecs_add_type (location_t loc, stru
*** 13134,13139 ****
--- 13135,13145 ----
  	      specs->typedef_p = true;
  	      specs->locations[cdw_typedef] = loc;
  	    }
+ 
+ 	  if (TREE_CODE (type) == RECORD_TYPE || TREE_CODE (type) == UNION_TYPE
+ 	      || TREE_CODE (type) == ENUMERAL_TYPE)
+ 	    mark_decl_used (TYPE_STUB_DECL (type), false);
+ 
  	  if (spec.expr)
  	    {
  	      if (specs->expr)
diff -Nrcpad gcc-16-20260606/gcc/c/c-typeck.cc gcc-16-20260613/gcc/c/c-typeck.cc
*** gcc-16-20260606/gcc/c/c-typeck.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/c/c-typeck.cc	Sat Jun 13 22:32:06 2026
*************** c_reconstruct_complex_type (tree type, t
*** 579,586 ****
  
  /* Helper function for c_canonical_type.  Check whether FIELD
     contains a pointer to a structure or union with tag,
!    possibly nested in other type derivations.  */
! static bool
  ptr_to_tagged_member (tree field)
  {
    gcc_assert (FIELD_DECL == TREE_CODE (field));
--- 579,587 ----
  
  /* Helper function for c_canonical_type.  Check whether FIELD
     contains a pointer to a structure or union with tag,
!    possibly nested in other type derivations, and return the
!    type of this nested structure or union.  */
! static tree
  ptr_to_tagged_member (tree field)
  {
    gcc_assert (FIELD_DECL == TREE_CODE (field));
*************** ptr_to_tagged_member (tree field)
*** 598,614 ****
    if (ptr_seen
        && RECORD_OR_UNION_TYPE_P (type)
        && NULL_TREE != c_type_tag (type))
!     return true;
  
!   return false;
  }
  
  /* For a record or union type, make necessary adaptations so that the
     type can be used as TYPE_CANONICAL.
  
     If the TYPE contains a pointer (possibly nested in other type
!    derivations) to a structure or union as a member, create a copy
!    and change such pointers to void pointers.  Otherwise, the middle-end
     gets confused when recording component aliases in the case where we
     have formed equivalency classes that include types for which these
     member pointers end up pointing to other structure or unions types
--- 599,615 ----
    if (ptr_seen
        && RECORD_OR_UNION_TYPE_P (type)
        && NULL_TREE != c_type_tag (type))
!     return type;
  
!   return NULL_TREE;
  }
  
  /* For a record or union type, make necessary adaptations so that the
     type can be used as TYPE_CANONICAL.
  
     If the TYPE contains a pointer (possibly nested in other type
!    derivations) to a structure or union as a member, create a copy and
!    change the nested type to an incomplete type.  Otherwise, the middle-end
     gets confused when recording component aliases in the case where we
     have formed equivalency classes that include types for which these
     member pointers end up pointing to other structure or unions types
*************** c_type_canonical (tree type)
*** 635,643 ****
    for (tree x = TYPE_FIELDS (type); x; x = DECL_CHAIN (x))
      {
        tree f = copy_node (x);
!       if (ptr_to_tagged_member (x))
! 	TREE_TYPE (f) = c_reconstruct_complex_type (TREE_TYPE (x),
! 						    ptr_type_node);
        *fields = f;
        fields = &DECL_CHAIN (f);
      }
--- 636,650 ----
    for (tree x = TYPE_FIELDS (type); x; x = DECL_CHAIN (x))
      {
        tree f = copy_node (x);
!       if (tree m = ptr_to_tagged_member (x))
! 	{
! 	  tree new_node = make_node (TREE_CODE (m));
! 	  TYPE_NAME (new_node) = TYPE_NAME (m);
! 	  SET_TYPE_STRUCTURAL_EQUALITY (new_node);
! 	  new_node = qualify_type (new_node, m);
! 	  TREE_TYPE (f) = c_reconstruct_complex_type (TREE_TYPE (x),
! 						      new_node);
! 	}
        *fields = f;
        fields = &DECL_CHAIN (f);
      }
*************** function_to_pointer_conversion (location
*** 2373,2379 ****
  
    tree exp2 = build_unary_op (loc, ADDR_EXPR, exp, false);
  
!   /* If the function is defined and known to not to require a non-local
       context, make sure no trampoline is generated.  */
    if (TREE_CODE (exp) == FUNCTION_DECL
        && DECL_INITIAL (exp) && !C_FUNC_NONLOCAL_CONTEXT (exp))
--- 2380,2386 ----
  
    tree exp2 = build_unary_op (loc, ADDR_EXPR, exp, false);
  
!   /* If the function is defined and known to not require a non-local
       context, make sure no trampoline is generated.  */
    if (TREE_CODE (exp) == FUNCTION_DECL
        && DECL_INITIAL (exp) && !C_FUNC_NONLOCAL_CONTEXT (exp))
diff -Nrcpad gcc-16-20260606/gcc/common/config/i386/cpuinfo.h gcc-16-20260613/gcc/common/config/i386/cpuinfo.h
*** gcc-16-20260606/gcc/common/config/i386/cpuinfo.h	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/common/config/i386/cpuinfo.h	Sat Jun 13 22:32:06 2026
*************** get_amd_cpu (struct __processor_model *c
*** 349,354 ****
--- 349,396 ----
    return cpu;
  }
  
+ /* Get the specific type of HYGON CPU and return HYGON CPU name.  Return
+    NULL for unknown HYGON CPU.  */
+ 
+ static inline const char *
+ get_hygon_cpu (struct __processor_model *cpu_model,
+ 	       struct __processor_model2 *cpu_model2,
+ 	       unsigned int *cpu_features2 __attribute__((unused)))
+ {
+   const char *cpu = NULL;
+   unsigned int family = cpu_model2->__cpu_family;
+   unsigned int model = cpu_model2->__cpu_model;
+ 
+   switch (family)
+     {
+     case 0x18:
+       cpu_model->__cpu_type = HYGONFAM18H;
+       if (model == 0x4)
+ 	{
+ 	  cpu = "c86-4g-m4";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m4");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M4;
+ 	}
+       else if (model == 0x6)
+ 	{
+ 	  cpu = "c86-4g-m6";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m6");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M6;
+ 	}
+       else if (model == 0x7)
+ 	{
+ 	  cpu = "c86-4g-m7";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m7");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7;
+ 	}
+       break;
+     default:
+       break;
+     }
+ 
+   return cpu;
+ }
+ 
  /* Get the specific type of Intel CPU and return Intel CPU name.  Return
     NULL for unknown Intel CPU.  */
  
*************** cpu_indicator_init (struct __processor_m
*** 1259,1264 ****
--- 1301,1321 ----
      cpu_model->__cpu_vendor = VENDOR_CYRIX;
    else if (vendor == signature_NSC_ebx)
      cpu_model->__cpu_vendor = VENDOR_NSC;
+   else if (vendor == signature_HYGON_ebx)
+     {
+       /* Adjust model and family for HYGON CPUS.  */
+       if (family == 0x0f)
+ 	{
+ 	  family += extended_family;
+ 	  model += extended_model;
+ 	}
+       cpu_model2->__cpu_family = family;
+       cpu_model2->__cpu_model = model;
+ 
+       /* Get CPU type.  */
+       get_hygon_cpu (cpu_model, cpu_model2, cpu_features2);
+       cpu_model->__cpu_vendor = VENDOR_HYGON;
+     }
    else
      cpu_model->__cpu_vendor = VENDOR_OTHER;
  
diff -Nrcpad gcc-16-20260606/gcc/common/config/i386/i386-common.cc gcc-16-20260613/gcc/common/config/i386/i386-common.cc
*** gcc-16-20260606/gcc/common/config/i386/i386-common.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/common/config/i386/i386-common.cc	Sat Jun 13 22:32:06 2026
*************** const char *const processor_names[] =
*** 2205,2211 ****
    "znver3",
    "znver4",
    "znver5",
!   "znver6"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 2205,2214 ----
    "znver3",
    "znver4",
    "znver5",
!   "znver6",
!   "c86-4g-m4",
!   "c86-4g-m6",
!   "c86-4g-m7"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
*************** const pta processor_alias_table[] =
*** 2473,2478 ****
--- 2476,2490 ----
    {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
      PTA_BTVER2,
      M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
+   {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
+     PTA_C86_4G_M4,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
+   {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
+     PTA_C86_4G_M6,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
+   {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
+     PTA_C86_4G_M7,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
  
    {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
      PTA_64BIT
*************** const pta processor_alias_table[] =
*** 2493,2502 ****
      M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
    {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
      M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
  };
  
  /* NB: processor_alias_table stops at the "generic" entry.  */
! unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
  unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
  
  /* Provide valid option values for -march and -mtune options.  */
--- 2505,2518 ----
      M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
    {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
      M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
+   {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+     M_VENDOR (VENDOR_HYGON), P_NONE},
+   {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+     M_CPU_TYPE (HYGONFAM18H), P_NONE},
  };
  
  /* NB: processor_alias_table stops at the "generic" entry.  */
! unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
  unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
  
  /* Provide valid option values for -march and -mtune options.  */
diff -Nrcpad gcc-16-20260606/gcc/common/config/i386/i386-cpuinfo.h gcc-16-20260613/gcc/common/config/i386/i386-cpuinfo.h
*** gcc-16-20260606/gcc/common/config/i386/i386-cpuinfo.h	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/common/config/i386/i386-cpuinfo.h	Sat Jun 13 22:32:06 2026
*************** enum processor_vendor
*** 30,35 ****
--- 30,36 ----
    VENDOR_INTEL = 1,
    VENDOR_AMD,
    VENDOR_ZHAOXIN,
+   VENDOR_HYGON,
    VENDOR_OTHER,
    VENDOR_CENTAUR,
    VENDOR_CYRIX,
*************** enum processor_types
*** 62,67 ****
--- 63,69 ----
    INTEL_GRANDRIDGE,
    INTEL_CLEARWATERFOREST,
    AMDFAM1AH,
+   HYGONFAM18H,
    CPU_TYPE_MAX,
    BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
  };
*************** enum processor_subtypes
*** 108,113 ****
--- 110,118 ----
    INTEL_COREI7_DIAMONDRAPIDS,
    INTEL_COREI7_NOVALAKE,
    AMDFAM1AH_ZNVER6,
+   HYGONFAM18H_C86_4G_M4,
+   HYGONFAM18H_C86_4G_M6,
+   HYGONFAM18H_C86_4G_M7,
    CPU_SUBTYPE_MAX
  };
  
diff -Nrcpad gcc-16-20260606/gcc/config/avr/avr.cc gcc-16-20260613/gcc/config/avr/avr.cc
*** gcc-16-20260606/gcc/config/avr/avr.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/avr/avr.cc	Sat Jun 13 22:32:06 2026
*************** avr_out_fract (rtx_insn *insn, rtx opera
*** 10541,10547 ****
  	{
  	  avr_asm_len ("clr __tmp_reg__" CR_TAB
  		       "sbrc %1,0"       CR_TAB
! 		       "dec __tmp_reg__", xop, plen, 1);
  	  sn = src.regno;
  	  if (sn < s0)
  	    {
--- 10541,10547 ----
  	{
  	  avr_asm_len ("clr __tmp_reg__" CR_TAB
  		       "sbrc %1,0"       CR_TAB
! 		       "dec __tmp_reg__", xop, plen, 3);
  	  sn = src.regno;
  	  if (sn < s0)
  	    {
*************** avr_out_fract (rtx_insn *insn, rtx opera
*** 10556,10562 ****
  	    avr_asm_len ("clt"                CR_TAB
  			 "bld __tmp_reg__,7"  CR_TAB
  			 "adc %0,__tmp_reg__",
! 			 &all_regs_rtx[s0], plen, 1);
  	  else
  	    avr_asm_len ("lsr __tmp_reg" CR_TAB
  			 "add %0,__tmp_reg__",
--- 10556,10562 ----
  	    avr_asm_len ("clt"                CR_TAB
  			 "bld __tmp_reg__,7"  CR_TAB
  			 "adc %0,__tmp_reg__",
! 			 &all_regs_rtx[s0], plen, 3);
  	  else
  	    avr_asm_len ("lsr __tmp_reg" CR_TAB
  			 "add %0,__tmp_reg__",
*************** avr_out_fract (rtx_insn *insn, rtx opera
*** 10755,10762 ****
  	  xop[2] = all_regs_rtx[s0];
  	  if (!lsb_in_tmp_reg && !MAY_CLOBBER (s0))
  	    avr_asm_len ("mov __tmp_reg__,%2", xop, plen, 1);
! 	  avr_asm_len ("tst %0" CR_TAB "brpl 0f",
! 		       &all_regs_rtx[src.regno_msb], plen, 2);
  	  if (!lsb_in_tmp_reg)
  	    {
  	      unsigned sn = src.regno;
--- 10755,10762 ----
  	  xop[2] = all_regs_rtx[s0];
  	  if (!lsb_in_tmp_reg && !MAY_CLOBBER (s0))
  	    avr_asm_len ("mov __tmp_reg__,%2", xop, plen, 1);
! 	  avr_asm_len ("tst %0" CR_TAB
! 		       "brpl 0f", &all_regs_rtx[src.regno_msb], plen, 2);
  	  if (!lsb_in_tmp_reg)
  	    {
  	      unsigned sn = src.regno;
diff -Nrcpad gcc-16-20260606/gcc/config/i386/c86-4g-m7.md gcc-16-20260613/gcc/config/i386/c86-4g-m7.md
*** gcc-16-20260606/gcc/config/i386/c86-4g-m7.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/config/i386/c86-4g-m7.md	Sat Jun 13 22:32:06 2026
***************
*** 0 ****
--- 1,2063 ----
+ ;; Copyright (C) 2026 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ ;;
+ 
+ ;; HYGON c86-4g-m7 Scheduling
+ ;; Modeling automatons for decoders, integer execution pipes,
+ ;; AGU pipes, branch, floating point execution, fp store units,
+ ;; integer and floating point dividers.  Split fpu1 and fpu3
+ ;; into their own automata to keep these units independent
+ ;; without increasing the main c86_4g_m7_fpu state space.
+ (define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu02, c86_4g_m7_fpu13, c86_4g_m7_idiv, c86_4g_m7_fdiv")
+ 
+ ;; Decoders unit has 4 decoders and all of them can decode fast path
+ ;; and vector type instructions.
+ (define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
+ 
+ ;; Currently blocking all decoders for vector path instructions as
+ ;; they are dispatched separetely as microcode sequence.
+ (define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
+ 
+ ;; Direct instructions can be issued to any of the four decoders.
+ (define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")
+ 
+ ;; Fix me: Need to revisit this later to simulate fast path double behavior.
+ (define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")
+ 
+ ;; Integer unit 4 ALU pipes.
+ (define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")
+ 
+ ;; One separated integer divider.
+ (define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")
+ 
+ ;; c86-4g-m7 has an additional branch unit.
+ (define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
+ (define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")
+ 
+ ;; 3 AGU pipes in c86-4g-m7
+ (define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
+ (define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")
+ 
+ ;; Load is 4 cycles.  We do not model reservation of load unit.
+ (define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
+ (define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")
+ 
+ ;; vectorpath (microcoded) instructions are single issue instructions.
+ ;; So, they occupy all the integer units.
+ (define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
+ 					 +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Floating point unit 4 FP pipes.
+ (define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu13")
+ (define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu13")
+ 
+ (define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ (define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
+ (define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
+ (define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
+ (define_reservation "c86-4g-m7-fpu_0_3" "c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3x2" "c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpu_1_3x3" "c86-4g-m7-fpu1*3|c86-4g-m7-fpu3*3")
+ (define_reservation "c86-4g-m7-fpu_1_3x6" "c86-4g-m7-fpu1*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu1*2|c86-4g-m7-fpu2*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpux4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu1*4|c86-4g-m7-fpu2*4|c86-4g-m7-fpu3*4")
+ (define_reservation "c86-4g-m7-fpux8" "c86-4g-m7-fpu0*8|c86-4g-m7-fpu1*8|c86-4g-m7-fpu2*8|c86-4g-m7-fpu3*8")
+ (define_reservation "c86-4g-m7-fpux6" "c86-4g-m7-fpu0*6|c86-4g-m7-fpu1*6|c86-4g-m7-fpu2*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux16" "c86-4g-m7-fpu0*16|c86-4g-m7-fpu1*16|c86-4g-m7-fpu2*16|c86-4g-m7-fpu3*16")
+ (define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
+ 					 +c86-4g-m7-fpu2+c86-4g-m7-fpu3
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Two FP dividers.
+ (define_cpu_unit "c86-4g-m7-fdiv1" "c86_4g_m7_fdiv")
+ (define_cpu_unit "c86-4g-m7-fdiv3" "c86_4g_m7_fdiv")
+ 
+ (define_reservation "c86-4g-m7-fp1fdiv1x4" "(c86-4g-m7-fpu1+c86-4g-m7-fdiv1)*4")
+ (define_reservation "c86-4g-m7-fp3fdiv3x4" "(c86-4g-m7-fpu3+c86-4g-m7-fdiv3)*4")
+ (define_reservation "c86-4g-m7-fdiv13" "(c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13" "(c86-4g-m7-fpu1+c86-4g-m7-fpu3+c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13x4" "c86-4g-m7-fp13div13*4")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x8" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*8)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*8)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x9" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*9)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*9)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x11" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*11)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*11)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*15)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*15)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)")
+ 
+ ;; IMOV/IMOVX
+ (define_insn_reservation "c86_4g_m7_imov_xchg" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_imovx_cwde" 2
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imovx")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "direct")
+ 				       (eq_attr "memory" "none"))))
+ 	     "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_store" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; PUSH
+ (define_insn_reservation "c86_4g_m7_push" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "push,sse")
+ 				  (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_push_mem" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 				 (and (eq_attr "type" "push")
+ 				  (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; POP
+ (define_insn_reservation "c86_4g_m7_pop" 4
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "pop")
+ 				  (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_pop_mem" 5
+ 	    (and (eq_attr "cpu" "c86_4g_m7")
+ 		 (and (eq_attr "type" "pop")
+ 		  (eq_attr "memory" "both")))
+ 	     "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; IMUL/IMULX
+ (define_insn_reservation "c86_4g_m7_imul" 3
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imul,imulx")
+ 				  (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu1")
+ 
+ (define_insn_reservation "c86_4g_m7_imul_load" 7
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imul")
+ 				  (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")
+ 
+ ;; IDIV
+ (define_insn_reservation "c86_4g_m7_idiv" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ ;; Integer/genaral Instructions
+ (define_insn_reservation "c86_4g_m7_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
+ 						    rotate,rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
+ 						    ishiftx,icmov,rotate,rotatex")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
+ 						    alu,icmov,ishift,negnot,alu1")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn2_store" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "icmp")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_both" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
+ 						    rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ ;; ALU1
+ (define_insn_reservation "c86_4g_m7_alu1_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_double_load" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; CALL/CALLV
+ (define_insn_reservation "c86_4g_m7_call" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "call,callv"))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store")
+ 
+ ;; IBR
+ (define_insn_reservation "c86_4g_m7_branch" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+ 
+ (define_insn_reservation "c86_4g_m7_branch_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+ 
+ ;; LEA
+ (define_insn_reservation "c86_4g_m7_lea" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "lea"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ ;; LEAVE
+ (define_insn_reservation "c86_4g_m7_leave" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "leave"))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ ;; STR
+ (define_insn_reservation "c86_4g_m7_str" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_str_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")
+ 
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 				       (eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*5")
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")
+ 
+ ;; SSEINS
+ (define_insn_reservation "c86_4g_m7_sse_insertimm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "2"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_insert" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "!2"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1*2")
+ 
+ ;; FCMOV
+ (define_insn_reservation "c86_4g_m7_fp_cmov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "fcmov"))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*3")
+ 
+ ;; FLD
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FST
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ ;; FILD
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FIST
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ ;; FSQRT
+ (define_insn_reservation "c86_4g_m7_fp_sqrt" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (eq_attr "c86_attr" "sqrt")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18")
+ 
+ ;; FPSPC
+ (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 				    (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_spc" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*6")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fmul")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")
+ 
+ ;; FDIV
+ (define_insn_reservation "c86_4g_m7_fp_div" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_div_load" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fsgn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "fsgn"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; FCMP
+ (define_insn_reservation "c86_4g_m7_fp_fcmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ ;; MMX
+ (define_insn_reservation "c86_4g_m7_fp_mmx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "mmx"))
+ 			 "c86-4g-m7-direct")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SADBW
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; PINSR
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; PERM
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux8")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					 (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux8")
+ 
+ ;; VINSERT
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					 (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0*2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")
+ 
+ ;; SHUF/MULTISHIFTQB
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ ;; SSELOGIC
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; CMPESTR
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux6")
+ 
+ ;; SSELOG
+ (define_insn_reservation "c86_4g_m7_avx512_log" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_log_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSELOG1
+ ;; VDBPSADBW
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ ;; ABS
+ (define_insn_reservation "c86_4g_m7_avx512_abs" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SIGN
+ (define_insn_reservation "c86_4g_m7_avx_sign" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sign_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ ;; BLEND/ABS/AES
+ (define_insn_reservation "c86_4g_m7_avx_blend" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_blend_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ 
+ ;; EXTR
+ (define_insn_reservation "c86_4g_m7_extr" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_extr_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSECOMI
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; SSEIMUL
+ (define_insn_reservation "c86_4g_m7_avx512_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ ;; SSEMOV
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				    (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				   (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sselog1")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; EXPAND
+ (define_insn_reservation "c86_4g_m7_avx512_expand" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ ;; MOVNT
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					(eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,mmxmov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; BLENDV
+ (define_insn_reservation "c86_4g_m7_avx512_blendv" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMOV2
+ (define_insn_reservation "c86_4g_m7_sse_mov2" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SSEISHFT
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ 
+ ;; SSEADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 				      (and (eq_attr "memory" "none")
+ 					   (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 				      (ior (eq_attr "memory" "load")
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; SUB/ADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; HADD/HSUB
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ ;; SSEIADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; AVG
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 				     (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux2")
+ 
+ ;; SSEMUL
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSEDIV
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ ;; SSECMP
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; VPTEST
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSECVT
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "!none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "register_operand")
+ 					       (match_operand:V8DF 1 "register_operand"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "memory_operand")
+ 					       (match_operand:V8DF 1 "memory_operand"))
+ 					  (eq_attr "memory" "!none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				     (and (eq_attr "mmx_isa" "base")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				    (and (eq_attr "mmx_isa" "base")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; CVTPI
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				    (and (not (eq_attr "mode" "SF,DI"))
+ 				     (and (eq_attr "mmx_isa" "native")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (not (eq_attr "mode" "SF,DI"))
+ 				    (and (eq_attr "mmx_isa" "native")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMULADD
+ (define_insn_reservation "c86_4g_m7_avx512_muladd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSE
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "prefix" "evex")
+ 				       (and (eq_attr "c86_decode" "direct")
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "c86_decode" "direct")
+ 				       (and (eq_attr "prefix" "evex")
+ 					    (eq_attr "memory" "load")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "length_immediate" "1")
+ 				     (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSE SQRT
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ ;; MSKLOG/MSKMOV
+ (define_insn_reservation "c86_4g_m7_avx512_msklog" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "direct")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "vector")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "r")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (ior (match_operand:V2DI 0 "register_operand" "v")
+ 					(match_operand:V4DI 0 "register_operand" "v"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (match_operand:V8DI 0 "register_operand" "v")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "k"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "r"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "memory_operand"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
diff -Nrcpad gcc-16-20260606/gcc/config/i386/c86-4g.md gcc-16-20260613/gcc/config/i386/c86-4g.md
*** gcc-16-20260606/gcc/config/i386/c86-4g.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/config/i386/c86-4g.md	Sat Jun 13 22:32:06 2026
***************
*** 0 ****
--- 1,1214 ----
+ ;; Copyright (C) 2026 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ ;;
+ 
+ 
+ (define_attr "c86_decode" "direct,vector,double"
+   (const_string "direct"))
+ 
+ (define_attr "c86_attr" "other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,
+ 			       sign,sadbw,insr,perm2,perm,insertx,shufx,madd,
+ 			       compress,sselogic,cmpestr,extr,vpmovx,expand,aes,
+ 			       hplus,ptest"
+   (const_string "other"))
+ 
+ ;; HYGON Scheduling
+ ;; Modeling automatons for decoders, integer execution pipes,
+ ;; AGU pipes, floating point execution units, integer and
+ ;; floating point dividers.  Split fp1 into its own automaton
+ ;; to keep this unit independent without increasing the main
+ ;; c86_4g_fp state space.
+ (define_automaton "c86_4g, c86_4g_ieu, c86_4g_fp024, c86_4g_fp1, c86_4g_agu, c86_4g_idiv, c86_4g_fdiv")
+ 
+ ;; Decoders unit has 4 decoders and all of them can decode fast path
+ ;; and vector type instructions.
+ (define_cpu_unit "c86-4g-decode0" "c86_4g")
+ (define_cpu_unit "c86-4g-decode1" "c86_4g")
+ (define_cpu_unit "c86-4g-decode2" "c86_4g")
+ (define_cpu_unit "c86-4g-decode3" "c86_4g")
+ 
+ ;; Currently blocking all decoders for vector path instructions as
+ ;; they are dispatched separetely as microcode sequence.
+ ;; Fix me: Need to revisit this.
+ (define_reservation "c86-4g-vector" "c86-4g-decode0+c86-4g-decode1+c86-4g-decode2+c86-4g-decode3")
+ 
+ ;; Direct instructions can be issued to any of the four decoders.
+ (define_reservation "c86-4g-direct" "c86-4g-decode0|c86-4g-decode1|c86-4g-decode2|c86-4g-decode3")
+ 
+ ;; Fix me: Need to revisit this later to simulate fast path double behavior.
+ (define_reservation "c86-4g-double" "c86-4g-direct")
+ 
+ ;; Integer unit 4 ALU pipes.
+ (define_cpu_unit "c86-4g-ieu0" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu1" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu2" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu3" "c86_4g_ieu")
+ (define_reservation "c86-4g-ieu" "c86-4g-ieu0|c86-4g-ieu1|c86-4g-ieu2|c86-4g-ieu3")
+ 
+ ;; One separated integer divider.
+ (define_cpu_unit "c86-4g-idiv" "c86_4g_idiv")
+ 
+ ;; 2 AGU pipes in c86_4g
+ ;; According to CPU diagram last AGU unit is used only for stores.
+ (define_cpu_unit "c86-4g-agu0" "c86_4g_agu")
+ (define_cpu_unit "c86-4g-agu1" "c86_4g_agu")
+ (define_reservation "c86-4g-agu-reserve" "c86-4g-agu0|c86-4g-agu1")
+ 
+ ;; Load is 4 cycles.  We do not model reservation of load unit.
+ ;;(define_reservation "c86-4g-load" "c86-4g-agu-reserve, nothing, nothing, nothing")
+ (define_reservation "c86-4g-load" "c86-4g-agu-reserve")
+ (define_reservation "c86-4g-store" "c86-4g-agu-reserve")
+ 
+ ;; vectorpath (microcoded) instructions are single issue instructions.
+ ;; So, they occupy all the integer units.
+ (define_reservation "c86-4g-ivector" "c86-4g-ieu0+c86-4g-ieu1
+ 				      +c86-4g-ieu2+c86-4g-ieu3
+ 				      +c86-4g-agu0+c86-4g-agu1")
+ 
+ ;; Floating point unit 4 FP pipes.
+ (define_cpu_unit "c86-4g-fp0" "c86_4g_fp024")
+ (define_cpu_unit "c86-4g-fp1" "c86_4g_fp1")
+ (define_cpu_unit "c86-4g-fp2" "c86_4g_fp024")
+ (define_cpu_unit "c86-4g-fp3" "c86_4g_fp024")
+ 
+ (define_reservation "c86-4g-fpu" "c86-4g-fp0|c86-4g-fp1|c86-4g-fp2|c86-4g-fp3")
+ 
+ (define_reservation "c86-4g-fvector" "c86-4g-fp0+c86-4g-fp1
+ 				      +c86-4g-fp2+c86-4g-fp3
+ 				      +c86-4g-agu0+c86-4g-agu1")
+ 
+ ;; One separated FP divider.
+ (define_cpu_unit "c86-4g-fdiv" "c86_4g_fdiv")
+ 
+ (define_reservation "c86-4g-fp1fdivx4" "(c86-4g-fp1+c86-4g-fdiv)*4")
+ 
+ ;; Call instruction
+ (define_insn_reservation "c86_4g_call" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "call,callv"))
+ 			 "c86-4g-double,c86-4g-store,c86-4g-ieu0+c86-4g-ieu3")
+ 
+ ;; General instructions
+ (define_insn_reservation "c86_4g_push" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "push")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-direct,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_push_load" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "push")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load+c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_pop" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "pop")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ (define_insn_reservation "c86_4g_pop_mem" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "pop")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-store")
+ 
+ ;; Leave
+ (define_insn_reservation "c86_4g_leave" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "leave"))
+ 			 "c86-4g-double,c86-4g-ieu+c86-4g-store")
+ 
+ ;; Integer Instructions or General instructions
+ ;; Multiplications
+ ;; Reg operands
+ (define_insn_reservation "c86_4g_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "imul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-ieu1")
+ 
+ (define_insn_reservation "c86_4g_imul_mem" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "imul")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-direct,c86-4g-load, c86-4g-ieu1")
+ 
+ ;; Divisions
+ ;; Reg operands
+ (define_insn_reservation "c86_4g_idiv_DI" 41
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "DI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*41")
+ 
+ (define_insn_reservation "c86_4g_idiv_SI" 25
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "SI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*25")
+ 
+ (define_insn_reservation "c86_4g_idiv_HI" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "HI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*17")
+ 
+ (define_insn_reservation "c86_4g_idiv_QI" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-ieu2,c86-4g-idiv*15")
+ 
+ ;; Mem operands
+ (define_insn_reservation "c86_4g_idiv_mem_DI" 45
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "DI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*41")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_SI" 29
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "SI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*25")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_HI" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "HI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*17")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_QI" 19
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*15")
+ 
+ ;; STR ISHIFT which are micro coded.
+ ;; Fix me: Latency need to be rechecked.
+ (define_insn_reservation "c86_4g_str_ishift" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "str,ishift")
+ 				   (eq_attr "memory" "both,store")))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; MOV - integer moves
+ (define_insn_reservation "c86_4g_load_imov_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_double_store" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-double,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "store"))))
+ 				   "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_load_imov_double_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct_load" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ ;; INTEGER/GENERAL instructions
+ ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
+ (define_insn_reservation "c86_4g_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_insn_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu")
+ 
+ ;; FIXME: The instructions matched here has only two operands, which means memory type can only be none, load or both.
+ ;; Store memory type handling should never take effect here?
+ (define_insn_reservation "c86_4g_insn_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_insn_both" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu,c86-4g-store")
+ 
+ ;; Special latency for multi type.
+ (define_insn_reservation "c86_4g_fp_fcomp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "none")
+ 				   (and (eq_attr "unit" "i387")
+ 					(eq_attr "type" "multi"))))
+ 			 "c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;; Fix me: Other vector type insns keeping latency 6 as of now.
+ (define_insn_reservation "c86_4g_ieu_vector" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "none")
+ 				   (and (eq_attr "unit" "!i387")
+ 					(eq_attr "type" "other,str,multi"))))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; ALU1 register operands.
+ (define_insn_reservation "c86_4g_alu1_vector" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "vector")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ (define_insn_reservation "c86_4g_alu1_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-double,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_alu1_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ ;; Branches : Fix me need to model conditional branches.
+ (define_insn_reservation "c86_4g_branch" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ibr")
+ 					(eq_attr "memory" "none")))
+ 			  "c86-4g-direct")
+ 
+ ;; Indirect branches check latencies.
+ (define_insn_reservation "c86_4g_indirect_branch_mem" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ibr")
+ 					(eq_attr "memory" "load")))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; LEA executes in ALU units with 1 cycle latency.
+ (define_insn_reservation "c86_4g_lea" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "lea"))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ ;;  Floating point
+ (define_insn_reservation "c86_4g_fp_cmov" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "fcmov"))
+ 			 "c86-4g-vector,c86-4g-fvector")
+ 
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct_store" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp2|c86-4g-fp3,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_double" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_double_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ ;; SQRT
+ (define_insn_reservation "c86_4g_fp_sqrt" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (eq_attr "c86_attr" "sqrt")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*18")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_sf" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,V4SF,V8SF")
+ 				   (and (eq_attr "memory" "none,unknown")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*10")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_sf_mem" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,V4SF,V8SF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*10")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_df" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DF,V2DF,V4DF")
+ 				   (and (eq_attr "memory" "none,unknown")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*16")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_df_mem" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DF,V2DF,V4DF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*16")
+ 
+ ;; RCP
+ (define_insn_reservation "c86_4g_sse_rcp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4SF,V8SF,SF")
+ 				   (and (eq_attr "memory" "none")
+ 					(and (eq_attr "c86_attr" "rcp")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_rcp_mem" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4SF,V8SF,SF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "rcp")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;; TODO: AGU?
+ (define_insn_reservation "c86_4g_fp_spc_direct" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fpspc")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp3")
+ 
+ ;; FABS
+ (define_insn_reservation "c86_4g_fp_absneg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "fsgn"))
+ 			 "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+ 
+ ;; FCMP
+ (define_insn_reservation "c86_4g_fp_fcmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				  (and (eq_attr "memory" "none")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "type" "fcmp"))))
+ 			 "c86-4g-double,c86-4g-fp0,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_fcmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "load")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "type" "fcmp"))))
+ 			 "c86-4g-double,c86-4g-load, c86-4g-fp0,c86-4g-fp1")
+ 
+ ;;FADD FSUB FMUL
+ (define_insn_reservation "c86_4g_fp_op_mul" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_mul_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_imul_load" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "load"))))
+ 			"c86-4g-double,c86-4g-load,c86-4g-fp0,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_div" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ (define_insn_reservation "c86_4g_fp_op_div_load" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ (define_insn_reservation "c86_4g_fp_op_idiv_load" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1*4,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
+ (define_insn_reservation "c86_4g_fp_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "mmx"))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_mmx_add" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxadd")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_add_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxadd")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_hadd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd1")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_hadd_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd1")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_cmp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_cmp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_cvt_pck_shuf" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_cvt_pck_shuf_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_shift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_shift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft,mmxmov")
+ 				   (eq_attr "memory" "store,both")))
+ 			  "c86-4g-direct,c86-4g-fp2,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_mmx_mul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_mul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; sseabs
+ (define_insn_reservation "c86_4g_sse_abs" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "abs")
+ 				   (and (eq_attr "type" "sselog1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_pinsr_reg" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 					(and (match_operand 2 "register_operand")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-ieu2,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_pinsr" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 					(and (not (match_operand 2 "register_operand"))
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_sign" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_sign_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_log1" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log1_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_extrq" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "prefix_data16" "1"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_movsdup" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "prefix" "vex"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_alignr" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_ishift" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "!1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_ishift_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "!1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_insertimm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "2"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_insert" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "!2"))))
+ 			 "c86-4g-direct,c86-4g-fpu,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_comi" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 				   (and (eq_attr "prefix" "!vex")
+ 					(and (eq_attr "prefix_extra" "0")
+ 					     (and (eq_attr "type" "ssecomi")
+ 						  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_load" 12
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "prefix_extra" "0")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_double" 2
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix" "vex")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(and (eq_attr "type" "ssecomi")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-double,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_double_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix" "vex")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(and (eq_attr "type" "ssecomi")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_test" 4
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_test_load" 11
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_avx256_test" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V8SF,V4DF,OI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_avx256_test_load" 15
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V8SF,V4DF,OI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ ;; SSE moves
+ ;; Fix me:  Need to revist this again some of the moves may be restricted
+ ;; to some fpu pipes.
+ 
+ ;; movnt doesn't touch cache, so latency modeling has little impact.
+ (define_insn_reservation "c86_4g_sse_movnt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ (define_insn_reservation "c86_4g_sse_movnt_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_mov" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "isa" "avx")
+ 					(and (eq_attr "type" "ssemov")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_avx_mov" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "TI")
+ 				   (and (eq_attr "isa" "avx")
+ 					(and (eq_attr "type" "ssemov")
+ 					     (and (match_operand:SI 1 "register_operand")
+ 						  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-direct,c86-4g-ieu2")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "0")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sseavx_blend" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "type" "ssemov,sselog1")
+ 				   (and (eq_attr "c86_attr" "blend,blendv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "store"))))
+ 			"c86-4g-direct,c86-4g-fpu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			       (and (eq_attr "type" "ssemov")
+ 				    (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-double,c86-4g-fpu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE max & min
+ (define_insn_reservation "c86_4g_sse_maxmin" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_maxmin_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_pmaxmin" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "TI,OI"))
+ 			      (and (eq_attr "type" "mmxadd,sseiadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_pmaxmin_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "TI,OI"))
+ 			      (and (eq_attr "type" "mmxadd,sseiadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE avg
+ (define_insn_reservation "c86_4g_sse_avg" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "c86_attr" "avg"))
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_avg_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "c86_attr" "avg"))
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+ 
+ ;;MMX sadbw
+ (define_insn_reservation "c86_4g_sse_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_sadbw_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; SSE add
+ (define_insn_reservation "c86_4g_sse_add" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "other"))))
+ 			 "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_sse_add_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "!maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_sse_fma" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_fma_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (eq_attr "memory" "load")))
+ 			"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_iadd" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_iadd_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE conversions.
+ (define_insn_reservation "c86_4g_ssecvtsf_si_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "type" "sseicvt")
+ 					(and (match_operand:SF 1 "memory_operand")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_ssecvtdf_si" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (match_operand:DF 1 "register_operand")
+ 					(and (eq_attr "type" "sseicvt")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-double,c86-4g-fp3,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_ssecvtdf_si_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "type" "sseicvt")
+ 					(and (match_operand:DF 1 "memory_operand")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+ 
+ ;; All other used ssecvt fp3 pipes
+ ;; Check: Need to revisit this again.
+ ;; Some SSE converts may use different pipe combinations.
+ (define_insn_reservation "c86_4g_ssecvt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_ssecvt_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ ;; SSE div
+ (define_insn_reservation "c86_4g_ssediv_ss_ps" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,SF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_ss_ps_load" 17
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,SF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_sd_pd" 13
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V2DF,DF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ (define_insn_reservation "c86_4g_ssediv_sd_pd_load" 20
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					       (eq_attr "mode" "V2DF,DF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_ps" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "type" "ssediv"))))
+ 			 "c86-4g-double,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_ps_load" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_pd" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4DF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_pd_load" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4DF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ ;; SSE MUL
+ (define_insn_reservation "c86_4g_ssemul_ss_ps" 3
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V8SF,V4SF,SF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_ss_ps_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V8SF,V4SF,SF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_sd_pd" 4
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V4DF,V2DF,DF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_sd_pd_load" 11
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V4DF,V2DF,DF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;;SSE imul
+ (define_insn_reservation "c86_4g_sseimul" 3
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "TI"))
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_avx256" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "TI"))
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_avx256_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_di" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DI")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "type" "sseimul"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_load_di" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; SSE compares
+ (define_insn_reservation "c86_4g_sse_cmp" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			       (and (eq_attr "type" "ssecmp")
+ 				    (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_avx256" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "none"))))
+ 			"c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_avx256_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_icmp" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_avx256" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_avx256_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fpu")
diff -Nrcpad gcc-16-20260606/gcc/config/i386/cpuid.h gcc-16-20260613/gcc/config/i386/cpuid.h
*** gcc-16-20260606/gcc/config/i386/cpuid.h	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/cpuid.h	Sat Jun 13 22:32:06 2026
***************
*** 235,240 ****
--- 235,244 ----
  #define signature_SHANGHAI_ecx	0x20206961
  #define signature_SHANGHAI_edx	0x68676e61
  
+ #define signature_HYGON_ebx	0x6f677948
+ #define signature_HYGON_ecx	0x656e6975
+ #define signature_HYGON_edx	0x6e65476e
+ 
  #ifndef __x86_64__
  /* At least one cpu (Winchip 2) does not set %ebx and %ecx
     for cpuid leaf 1. Forcibly zero the two registers before
diff -Nrcpad gcc-16-20260606/gcc/config/i386/driver-i386.cc gcc-16-20260613/gcc/config/i386/driver-i386.cc
*** gcc-16-20260606/gcc/config/i386/driver-i386.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/driver-i386.cc	Sat Jun 13 22:32:06 2026
*************** const char *host_detect_local_cpu (int a
*** 501,506 ****
--- 501,516 ----
        else
  	processor = PROCESSOR_PENTIUM;
      }
+   else if (vendor == VENDOR_HYGON)
+     {
+       processor = PROCESSOR_GENERIC;
+       if (model == 4)
+ 	processor = PROCESSOR_C86_4G_M4;
+       else if (model == 6)
+ 	processor = PROCESSOR_C86_4G_M6;
+       else if (model >= 7)
+ 	processor = PROCESSOR_C86_4G_M7;
+     }
    else if (vendor == VENDOR_CENTAUR)
      {
        processor = PROCESSOR_GENERIC;
*************** const char *host_detect_local_cpu (int a
*** 850,855 ****
--- 860,874 ----
      case PROCESSOR_SHIJIDADAO:
        cpu = "shijidadao";
        break;
+     case PROCESSOR_C86_4G_M4:
+       cpu = "c86-4g-m4";
+       break;
+     case PROCESSOR_C86_4G_M6:
+       cpu = "c86-4g-m6";
+       break;
+     case PROCESSOR_C86_4G_M7:
+       cpu = "c86-4g-m7";
+       break;
  
      default:
        /* Use something reasonable.  */
diff -Nrcpad gcc-16-20260606/gcc/config/i386/i386-c.cc gcc-16-20260613/gcc/config/i386/i386-c.cc
*** gcc-16-20260606/gcc/config/i386/i386-c.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/i386-c.cc	Sat Jun 13 22:32:06 2026
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 303,309 ****
        def_or_undef (parse_in, "__novalake");
        def_or_undef (parse_in, "__novalake__");
        break;
! 
      /* use PROCESSOR_max to not set/unset the arch macro.  */
      case PROCESSOR_max:
        break;
--- 303,320 ----
        def_or_undef (parse_in, "__novalake");
        def_or_undef (parse_in, "__novalake__");
        break;
!     case PROCESSOR_C86_4G_M4:
!       def_or_undef (parse_in, "__c86_4g_m4");
!       def_or_undef (parse_in, "__c86_4g_m4__");
!       break;
!     case PROCESSOR_C86_4G_M6:
!       def_or_undef (parse_in, "__c86_4g_m6");
!       def_or_undef (parse_in, "__c86_4g_m6__");
!       break;
!     case PROCESSOR_C86_4G_M7:
!       def_or_undef (parse_in, "__c86_4g_m7");
!       def_or_undef (parse_in, "__c86_4g_m7__");
!       break;
      /* use PROCESSOR_max to not set/unset the arch macro.  */
      case PROCESSOR_max:
        break;
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 512,517 ****
--- 523,537 ----
      case PROCESSOR_NOVALAKE:
        def_or_undef (parse_in, "__tune_novalake__");
        break;
+     case PROCESSOR_C86_4G_M4:
+       def_or_undef (parse_in, "__tune_c86_4g_m4__");
+       break;
+     case PROCESSOR_C86_4G_M6:
+       def_or_undef (parse_in, "__tune_c86_4g_m6__");
+       break;
+     case PROCESSOR_C86_4G_M7:
+       def_or_undef (parse_in, "__tune_c86_4g_m7__");
+       break;
      case PROCESSOR_INTEL:
      case PROCESSOR_GENERIC:
        break;
diff -Nrcpad gcc-16-20260606/gcc/config/i386/i386-options.cc gcc-16-20260613/gcc/config/i386/i386-options.cc
*** gcc-16-20260606/gcc/config/i386/i386-options.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/i386-options.cc	Sat Jun 13 22:32:06 2026
*************** along with GCC; see the file COPYING3.
*** 185,190 ****
--- 185,194 ----
  #define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
  #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \
  			| m_ZNVER)
+ #define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)
+ #define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)
+ #define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)
+ #define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7)
  
  #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
  
*************** static const struct processor_costs *pro
*** 814,820 ****
    &znver3_cost,		/* PROCESSOR_ZNVER3.		*/
    &znver4_cost,		/* PROCESSOR_ZNVER4.		*/
    &znver5_cost,		/* PROCESSOR_ZNVER5.		*/
!   &znver5_cost		/* PROCESSOR_ZNVER6.		*/
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 818,827 ----
    &znver3_cost,		/* PROCESSOR_ZNVER3.		*/
    &znver4_cost,		/* PROCESSOR_ZNVER4.		*/
    &znver5_cost,		/* PROCESSOR_ZNVER5.		*/
!   &znver5_cost,		/* PROCESSOR_ZNVER6.		*/
!   &c86_4g_m4_cost,	/* PROCESSOR_C86_4G_M4.		*/
!   &c86_4g_m6_cost,	/* PROCESSOR_C86_4G_M6.		*/
!   &c86_4g_m7_cost	/* PROCESSOR_C86_4G_M7.		*/
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
diff -Nrcpad gcc-16-20260606/gcc/config/i386/i386.cc gcc-16-20260613/gcc/config/i386/i386.cc
*** gcc-16-20260606/gcc/config/i386/i386.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/i386.cc	Sat Jun 13 22:32:06 2026
*************** ix86_reassociation_width (unsigned int o
*** 25829,25835 ****
        /* Znver1-4 Integer vector instructions execute in FP unit
  	 and can execute 3 additions and one multiplication per cycle.  */
        if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
! 	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
--- 25829,25838 ----
        /* Znver1-4 Integer vector instructions execute in FP unit
  	 and can execute 3 additions and one multiplication per cycle.  */
        if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
! 	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
! 	   || ix86_tune == PROCESSOR_C86_4G_M4
! 	   || ix86_tune == PROCESSOR_C86_4G_M6
! 	   || ix86_tune == PROCESSOR_C86_4G_M7)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
diff -Nrcpad gcc-16-20260606/gcc/config/i386/i386.h gcc-16-20260613/gcc/config/i386/i386.h
*** gcc-16-20260606/gcc/config/i386/i386.h	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/i386.h	Sat Jun 13 22:32:06 2026
*************** enum processor_type
*** 2385,2390 ****
--- 2385,2393 ----
    PROCESSOR_ZNVER4,
    PROCESSOR_ZNVER5,
    PROCESSOR_ZNVER6,
+   PROCESSOR_C86_4G_M4,
+   PROCESSOR_C86_4G_M6,
+   PROCESSOR_C86_4G_M7,
    PROCESSOR_max
  };
  
*************** constexpr wide_int_bitmask PTA_LUJIAZUI
*** 2548,2553 ****
--- 2551,2571 ----
  constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2
    | PTA_F16C | PTA_FMA | PTA_SHA;
  
+ constexpr wide_int_bitmask PTA_C86_4G_M4 = PTA_64BIT | PTA_MMX | PTA_SSE
+   | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
+   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+   | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+   | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX
+   | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+   | PTA_SHA | PTA_LZCNT | PTA_POPCNT;
+ constexpr wide_int_bitmask PTA_C86_4G_M6 = PTA_C86_4G_M4;
+ constexpr wide_int_bitmask PTA_C86_4G_M7 = PTA_C86_4G_M4 | PTA_AVX512F
+   | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
+   | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
+   | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ
+   | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ
+   | PTA_WBNOINVD | PTA_CLWB;
+ 
  #ifndef GENERATOR_FILE
  
  #include "insn-attr-common.h"
diff -Nrcpad gcc-16-20260606/gcc/config/i386/i386.md gcc-16-20260613/gcc/config/i386/i386.md
*** gcc-16-20260606/gcc/config/i386/i386.md	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/i386.md	Sat Jun 13 22:32:06 2026
***************
*** 530,536 ****
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5,znver6"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
--- 530,536 ----
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
***************
*** 1427,1432 ****
--- 1427,1434 ----
  (include "haswell.md")
  (include "lujiazui.md")
  (include "yongfeng.md")
+ (include "c86-4g.md")
+ (include "c86-4g-m7.md")
  
  
  ;; Operand and operator predicates and constraints
***************
*** 2038,2043 ****
--- 2040,2046 ----
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "znver1_decode" "double")])
  
  (define_insn "*cmpx<unord><MODEF:mode>"
***************
*** 2091,2096 ****
--- 2094,2100 ----
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "double")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set (attr "enabled")
       (if_then_else
         (match_test ("SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"))
***************
*** 2482,2487 ****
--- 2486,2492 ----
      }
  }
    [(set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+    (set_attr "c86_attr" "sselogic,sselogic,*,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 2506,2511 ****
--- 2511,2517 ----
  }
    [(set_attr "isa" "*,avx2,*,*")
     (set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+    (set_attr "c86_attr" "sselogic,sselogic,*,*")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
  
***************
*** 2548,2553 ****
--- 2554,2563 ----
  	      (const_string "sselog1")
  	   ]
  	   (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "2,3")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 2691,2696 ****
--- 2701,2710 ----
  	      (const_string "lea")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "12")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "modrm")
       (if_then_else
         (and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
***************
*** 2911,2916 ****
--- 2925,2934 ----
  	      (const_string "lea")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "8")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 3085,3090 ****
--- 3103,3112 ----
  	      (const_string "imovx")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "11")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
  	(cond [(eq_attr "alternative" "4,5,6,7,8")
  		 (const_string "vex")
***************
*** 3366,3371 ****
--- 3388,3394 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")])
  
  (define_insn "*swap<mode>"
***************
*** 3391,3396 ****
--- 3414,3420 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")])
  
  (define_peephole2
***************
*** 4068,4073 ****
--- 4092,4098 ----
  }
    [(set_attr "isa" "*,*,*,x64,x64")
     (set_attr "type" "sselog1,ssemov,ssemov,multi,multi")
+    (set_attr "c86_attr" "sselogic,*,*,*,*")
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 4239,4244 ****
--- 4264,4273 ----
  		 (const_string "sselog1")
  	      ]
  	      (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "12,16")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "modrm")
       (if_then_else (eq_attr "alternative" "11")
         (const_string "0")
***************
*** 4411,4416 ****
--- 4440,4449 ----
  		 (const_string "mmxmov")
  	      ]
  	      (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "5")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 4759,4764 ****
--- 4792,4801 ----
  	      (const_string "mskmov")
  	   ]
  	   (const_string "imovx")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "10,11")
+        (const_string "vpmovx")
+        (const_string "*")))
     (set (attr "prefix_extra")
       (if_then_else (eq_attr "alternative" "10,11")
         (const_string "1")
***************
*** 5168,5173 ****
--- 5205,5214 ----
       (if_then_else (eq_attr "prefix_0f" "0")
  	(const_string "double")
  	(const_string "direct")))
+    (set (attr "c86_decode")
+      (if_then_else (eq_attr "prefix_0f" "0")
+ 	(const_string "double")
+ 	(const_string "direct")))
     (set (attr "modrm")
       (if_then_else (eq_attr "prefix_0f" "0")
  	(const_string "0")
***************
*** 6075,6080 ****
--- 6116,6122 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "<MODE>")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  (define_insn "float<SWI48x:mode>xf2"
***************
*** 6085,6090 ****
--- 6127,6133 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "XF")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  (define_expand "float<SWI48x:mode><MODEF:mode>2"
***************
*** 6119,6124 ****
--- 6162,6168 ----
     (set_attr "amdfam10_decode" "*,vector,double")
     (set_attr "bdver1_decode" "*,double,direct")
     (set_attr "znver1_decode" "double,*,*")
+    (set_attr "c86_decode" "double,*,*")
     (set_attr "fp_int_src" "true")
     (set (attr "enabled")
       (if_then_else
***************
*** 6157,6162 ****
--- 6201,6207 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "<MODEF:MODE>")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  ;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory
***************
*** 12930,12935 ****
--- 12975,12981 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Turn *anddi_1 into *andsi_1_zext if possible.
***************
*** 13965,13970 ****
--- 14011,14017 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn_and_split "*xordi_1_btc"
***************
*** 13989,13994 ****
--- 14036,14042 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask)
***************
*** 19168,19173 ****
--- 19216,19222 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ;; Avoid useless masking of count operand.
***************
*** 19236,19241 ****
--- 19285,19291 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ;; Avoid useless masking of count operand.
***************
*** 19377,19382 ****
--- 19427,19433 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn "*btrq_imm"
***************
*** 19390,19395 ****
--- 19441,19447 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn "*btcq_imm"
***************
*** 19403,19408 ****
--- 19455,19461 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Allow Nocona to avoid these instructions if a register is available.
***************
*** 21382,21387 ****
--- 21435,21441 ----
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "btver2_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ; False dependency happens when destination is only updated by tzcnt,
***************
*** 21401,21406 ****
--- 21455,21461 ----
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "btver2_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "*bsf<mode>_1"
***************
*** 21415,21420 ****
--- 21470,21476 ----
     (set_attr "prefix_0f" "1")
     (set_attr "btver2_decode" "double")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "<MODE>")])
  
  (define_insn_and_split "ctz<mode>2"
***************
*** 21477,21482 ****
--- 21533,21539 ----
      gcc_unreachable ();
  }
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "<MODE>")])
***************
*** 21502,21507 ****
--- 21559,21565 ----
       (clobber (reg:CC FLAGS_REG))])]
    "ix86_expand_clear (operands[0]);"
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "SI")])
***************
*** 21522,21527 ****
--- 21580,21586 ----
    "TARGET_BMI && TARGET_64BIT"
    "tzcnt{l}\t{%1, %k0|%k0, %1}"
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "SI")])
***************
*** 21599,21604 ****
--- 21658,21664 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr_rex64_1"
***************
*** 21611,21616 ****
--- 21671,21677 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr_rex64_1_zext"
***************
*** 21626,21631 ****
--- 21687,21693 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr"
***************
*** 21640,21645 ****
--- 21702,21708 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  (define_insn "bsr_1"
***************
*** 21652,21657 ****
--- 21715,21721 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  (define_insn "bsr_zext_1"
***************
*** 21666,21671 ****
--- 21730,21736 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  ; As bsr is undefined behavior on zero and for other input
***************
*** 22983,22988 ****
--- 23048,23054 ----
     (set_attr "pent_pair" "np,*,*")
     (set_attr "athlon_decode" "vector,*,*")
     (set_attr "amdfam10_decode" "double,*,*")
+    (set_attr "c86_decode" "vector,*,*")
     (set_attr "bdver1_decode" "double,*,*")
     (set_attr "mode" "QI,HI,HI")])
  
***************
*** 22995,23000 ****
--- 23061,23067 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")
     (set_attr "mode" "QI")])
  
***************
*** 23019,23024 ****
--- 23086,23092 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")
     (set_attr "mode" "QI")])
  
***************
*** 24099,24104 ****
--- 24167,24173 ----
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
     (set_attr "athlon_decode" "direct")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "direct")])
  
***************
*** 24267,24272 ****
--- 24336,24342 ----
    "fprem"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "fmodxf3"
***************
*** 24339,24344 ****
--- 24409,24415 ----
    "fprem1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "remainderxf3"
***************
*** 24414,24419 ****
--- 24485,24491 ----
    "f<sincos>"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "<sincos><mode>2"
***************
*** 24445,24450 ****
--- 24517,24523 ----
    "fsincos"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "sincos<mode>3"
***************
*** 24478,24483 ****
--- 24551,24557 ----
    "fptan"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "tanxf2"
***************
*** 24520,24525 ****
--- 24594,24600 ----
    "fpatan"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "atan2<mode>3"
***************
*** 24823,24828 ****
--- 24898,24904 ----
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "logxf2"
***************
*** 24920,24925 ****
--- 24996,25002 ----
    "fyl2xp1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "log1pxf2"
***************
*** 24960,24965 ****
--- 25037,25043 ----
    "fxtract"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "logbxf2"
***************
*** 25040,25045 ****
--- 25118,25124 ----
    "f2xm1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_insn "fscalexf4_i387"
***************
*** 25055,25060 ****
--- 25134,25140 ----
    "fscale"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "expNcorexf3"
***************
*** 25373,25378 ****
--- 25453,25459 ----
    "frndint"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "rinthf2"
***************
*** 27191,27196 ****
--- 27272,27278 ----
     v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "prefix" "orig,vex")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "type" "sseadd")
     (set_attr "mode" "<MODE>")])
  
***************
*** 27235,27240 ****
--- 27317,27323 ----
     v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "prefix" "orig,maybe_evex")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "type" "sseadd")
     (set_attr "mode" "<MODE>")])
  
diff -Nrcpad gcc-16-20260606/gcc/config/i386/mmx.md gcc-16-20260613/gcc/config/i386/mmx.md
*** gcc-16-20260606/gcc/config/i386/mmx.md	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/mmx.md	Sat Jun 13 22:32:06 2026
***************
*** 664,669 ****
--- 664,670 ----
    [(set_attr "isa" "*,x64")
     (set_attr "mmx_isa" "native,*")
     (set_attr "type" "mmxmov,ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "DI")])
  
  (define_expand "movq_<mode>_to_sse"
***************
*** 1324,1329 ****
--- 1325,1331 ----
     vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 1344,1349 ****
--- 1346,1352 ----
     vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 3599,3604 ****
--- 3602,3608 ----
    [(set_attr "isa" "*,sse2_noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "mmxmul,sseiadd,sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "mode" "DI,TI,TI")])
  
  (define_expand "mmx_pmulhrwv4hi3"
***************
*** 4346,4351 ****
--- 4350,4356 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 4422,4427 ****
--- 4427,4433 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5040,5045 ****
--- 5046,5052 ----
    "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5072,5077 ****
--- 5079,5085 ----
    "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5104,5109 ****
--- 5112,5118 ----
    "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5130,5135 ****
--- 5139,5145 ----
    "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5306,5311 ****
--- 5316,5322 ----
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
***************
*** 5345,5350 ****
--- 5356,5362 ----
    [(set_attr "isa" "*,sse2_noavx,avx,sse4")
     (set_attr "mmx_isa" "native,*,*,*")
     (set_attr "type" "mmxcvt,sselog,sselog,sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "mode" "DI,TI,TI,TI")])
  
***************
*** 5395,5400 ****
--- 5407,5413 ----
  }
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 5417,5422 ****
--- 5430,5436 ----
     (set_attr "addr" "*,*,gpr16,*")
     (set_attr "mmx_isa" "native,*,*,*")
     (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
     (set_attr "mode" "DI,TI,TI,TI")])
***************
*** 5452,5457 ****
--- 5466,5472 ----
     (set_attr "addr" "*,*,gpr16,*,*,*")
     (set_attr "mmx_isa" "native,*,*,*,*,*")
     (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,extr,*,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
     (set_attr "mode" "DI,TI,TI,TI,TI,TI")])
***************
*** 5470,5475 ****
--- 5485,5491 ----
    [(set_attr "isa" "*,sse2")
     (set_attr "mmx_isa" "native,*")
     (set_attr "type" "mmxcvt,sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex")
     (set_attr "mode" "DI,TI")])
***************
*** 5488,5493 ****
--- 5504,5510 ----
    [(set_attr "isa" "noavx,noavx,avx,avx")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 5503,5508 ****
--- 5520,5526 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 5629,5634 ****
--- 5647,5653 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5647,5652 ****
--- 5666,5672 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5829,5834 ****
--- 5849,5855 ----
  		      (const_string "*")))
     (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
     (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
+    (set_attr "c86_attr" "*,extr,extr,*,*,*,*,*")
     (set (attr "length_immediate")
       (if_then_else (eq_attr "alternative" "1,2,3,4")
  		   (const_string "1")
***************
*** 5856,5861 ****
--- 5877,5883 ----
    "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 6010,6015 ****
--- 6032,6038 ----
  }
    [(set_attr "isa" "noavx,avx,sse4")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "mode" "TI")])
  
***************
*** 6062,6067 ****
--- 6085,6091 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 6080,6085 ****
--- 6104,6110 ----
    [(set_attr "isa" "*,sse4_noavx,avx")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "TI")])
***************
*** 6113,6118 ****
--- 6138,6144 ----
    [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,*,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 6126,6131 ****
--- 6152,6158 ----
    "TARGET_SSE2"
    "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "TI")])
***************
*** 6144,6149 ****
--- 6171,6177 ----
    [(set_attr "isa" "noavx,noavx,avx,avx")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 6159,6164 ****
--- 6187,6193 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 6511,6516 ****
--- 6540,6546 ----
    [(set_attr "isa" "*,sse2_noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "mmxshft,sseiadd,sseiadd")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "mode" "DI,TI,TI")])
  
  (define_expand "reduc_<code>_scal_<mode>"
***************
*** 6890,6895 ****
--- 6920,6926 ----
    "maskmovq\t{%2, %1|%1, %2}"
    [(set_attr "type" "mmxcvt")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_int_iterator EMMS
diff -Nrcpad gcc-16-20260606/gcc/config/i386/sse.md gcc-16-20260613/gcc/config/i386/sse.md
*** gcc-16-20260606/gcc/config/i386/sse.md	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/sse.md	Sat Jun 13 22:32:06 2026
***************
*** 1794,1799 ****
--- 1794,1804 ----
      }
  }
    [(set_attr "type" "ssemov")
+    (set (attr "c86_attr")
+      (if_then_else (and (match_test "REG_P (operands[1])")
+ 			(match_test "REGNO (operands[1]) != REGNO (operands[0])"))
+        (const_string "blend")
+        (const_string "*")))
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 1808,1813 ****
--- 1813,1819 ----
      vmovdqu<ssescalarsize>\t{%2, %0%{%3%}%N1|%0%{%3%}%N1, %2}
      vpblendm<sseintmodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "*,blend")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 2034,2039 ****
--- 2040,2046 ----
    "TARGET_SSE2"
    "movnti\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix_data16" "0")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2045,2050 ****
--- 2052,2058 ----
    "TARGET_SSE"
    "%vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2060,2065 ****
--- 2068,2074 ----
         (match_test "TARGET_AVX")
       (const_string "*")
       (const_string "1")))
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 2359,2364 ****
--- 2368,2374 ----
    "ktest<mskmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "mode" "<MODE>")
     (set_attr "type" "msklog")
+    (set_attr "c86_decode" "vector")
     (set_attr "prefix" "vex")])
  
  (define_insn "*kortest<mode>"
***************
*** 2371,2376 ****
--- 2381,2387 ----
    "kortest<mskmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "mode" "<MODE>")
     (set_attr "type" "msklog")
+    (set_attr "c86_decode" "vector")
     (set_attr "prefix" "vex")])
  
  (define_insn "kortest<mode>_ccc"
***************
*** 2939,2944 ****
--- 2950,2956 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2958,2963 ****
--- 2970,2976 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "SF")])
  
***************
*** 2978,2983 ****
--- 2991,2997 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "SF")])
  
***************
*** 3027,3032 ****
--- 3041,3047 ----
    "TARGET_AVX512F"
    "vrcp14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3041,3046 ****
--- 3056,3062 ----
    "TARGET_AVX512F"
    "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3058,3063 ****
--- 3074,3080 ----
    "TARGET_AVX512F"
    "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3093,3098 ****
--- 3110,3116 ----
     (set_attr "type" "sse")
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3112,3117 ****
--- 3130,3136 ----
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "prefix" "<round_scalar_prefix>")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_insn "*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>"
***************
*** 3131,3136 ****
--- 3150,3156 ----
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "prefix" "<round_scalar_prefix>")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_expand "rsqrt<mode>2"
***************
*** 3181,3186 ****
--- 3201,3207 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3195,3200 ****
--- 3216,3222 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3212,3217 ****
--- 3234,3240 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3336,3341 ****
--- 3359,3365 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<mask_prefix3>")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3469,3474 ****
--- 3493,3499 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<mask_prefix3>")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3493,3498 ****
--- 3518,3524 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set (attr "prefix")
       (cond [(eq_attr "alternative" "0")
  	      (const_string "orig")
***************
*** 3540,3545 ****
--- 3566,3572 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sse")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<round_saeonly_scalar_prefix>")
     (set_attr "mode" "<ssescalarmode>")])
  
***************
*** 3736,3741 ****
--- 3763,3769 ----
    "TARGET_AVX"
    "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix" "vex")
     (set_attr "mode" "V4DF")])
***************
*** 3781,3786 ****
--- 3809,3815 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "*,gpr16")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3803,3808 ****
--- 3832,3838 ----
     vhsubpd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "*,gpr16")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
***************
*** 3823,3828 ****
--- 3853,3859 ----
     vhaddpd\t{%1, %1, %0|%0, %1, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3841,3846 ****
--- 3872,3878 ----
     vhsubpd\t{%1, %1, %0|%0, %1, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3884,3889 ****
--- 3916,3922 ----
    "TARGET_AVX"
    "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix" "vex")
     (set_attr "mode" "V8SF")])
***************
*** 3915,3920 ****
--- 3948,3954 ----
     vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix" "orig,vex")
***************
*** 4253,4258 ****
--- 4287,4293 ----
    "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
    "vreduce<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 4269,4274 ****
--- 4304,4310 ----
    "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
    "vreduce<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 4937,4942 ****
--- 4973,4979 ----
     vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
     vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
    [(set_attr "type" "ssecmp")
+    (set_attr "c86_attr" "*,ptest")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 5026,5031 ****
--- 5063,5069 ----
     vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
     vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
    [(set_attr "type" "ssecmp")
+    (set_attr "c86_attr" "*,ptest")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 5635,5640 ****
--- 5673,5679 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512dq,avx512f")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,maybe_vex,evex,evex")
     (set (attr "mode")
  	(cond [(and (match_test "<mask_applied>")
***************
*** 5686,5691 ****
--- 5725,5731 ----
    return "";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set (attr "mode")
          (if_then_else (match_test "TARGET_AVX512DQ")
***************
*** 5762,5767 ****
--- 5802,5808 ----
  }
    [(set_attr "isa" "noavx,avx,avx512dq,avx512f")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,maybe_evex,evex,evex")
     (set (attr "mode")
  	(cond [(and (match_test "<mask_applied>")
***************
*** 5809,5814 ****
--- 5850,5856 ----
    return "";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set (attr "mode")
          (if_then_else (match_test "TARGET_AVX512DQ")
***************
*** 5926,5931 ****
--- 5968,5974 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,vex,evex,evex")
     (set (attr "mode")
  	(cond [(eq_attr "alternative" "2")
***************
*** 6056,6061 ****
--- 6099,6105 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,vex,evex,evex")
     (set (attr "mode")
  	(cond [(eq_attr "alternative" "2")
***************
*** 6118,6123 ****
--- 6162,6168 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 8860,8865 ****
--- 8905,8911 ----
     (set_attr "bdver1_decode" "double,direct,*")
     (set_attr "btver2_decode" "double,double,double")
     (set_attr "znver1_decode" "double,double,double")
+    (set_attr "c86_decode" "double,double,double")
     (set (attr "length_vex")
  	(if_then_else
  	  (and (match_test "<MODE>mode == DImode")
***************
*** 9321,9326 ****
--- 9367,9373 ----
     (set_attr "bdver1_decode" "double,direct,*")
     (set_attr "btver2_decode" "double,double,double")
     (set_attr "znver1_decode" "double,double,double")
+    (set_attr "c86_decode" "double,double,double")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "DF")])
  
***************
*** 12250,12255 ****
--- 12297,12306 ----
  	      (const_string "ssemov2")
  	   ]
  	   (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "9,10,11")
+ 		   (const_string "insr")
+ 		   (const_string "*")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "9,10")
  		   (const_string "gpr16")
***************
*** 12324,12329 ****
--- 12375,12387 ----
       (if_then_else (eq_attr "alternative" "0,1,2,3,6,7,10")
  		   (const_string "ssemov")
  		   (const_string "sselog")))
+    (set (attr "c86_attr")
+ 	(cond [(eq_attr "alternative" "6,7,10")
+ 		 (const_string "blend")
+ 	       (eq_attr "alternative" "4,5,8,9,11,12")
+ 		 (const_string "insr")
+ 	      ]
+ 	      (const_string "*")))
     (set (attr "prefix_data16")
       (if_then_else (eq_attr "alternative" "4,5")
  		   (const_string "1")
***************
*** 12692,12697 ****
--- 12750,12756 ----
    [(set_attr "isa" "noavx,noavx,avx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*,*,*")
     (set_attr "type" "sselog,sselog,sselog,*,*")
+    (set_attr "c86_attr" "extr,extr,extr,*,*")
     (set_attr "prefix_data16" "1,1,1,*,*")
     (set_attr "prefix_extra" "1,1,1,*,*")
     (set_attr "length_immediate" "1,1,1,*,*")
***************
*** 13591,13596 ****
--- 13650,13656 ----
    [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,other,other")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "TI")])
  
***************
*** 14381,14386 ****
--- 14441,14447 ----
    "TARGET_AVX512F"
    "valign<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
    [(set_attr "prefix" "evex")
+    (set_attr "c86_attr" "shufx")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_mode_attr vec_extract_imm_predicate
***************
*** 16996,17001 ****
--- 17057,17063 ----
     "TARGET_AVX512BW && <mask_mode512bit_condition>"
     "vpmaddwd\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 17067,17072 ****
--- 17129,17135 ----
    "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
  
***************
*** 17125,17130 ****
--- 17188,17194 ----
     vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,vex")
***************
*** 17992,17997 ****
--- 18056,18062 ----
    "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
***************
*** 18033,18038 ****
--- 18098,18104 ----
    "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 18044,18049 ****
--- 18110,18116 ----
    "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 18142,18147 ****
--- 18209,18215 ----
     vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix_extra" "1")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 18158,18163 ****
--- 18226,18232 ----
     vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
***************
*** 18226,18231 ****
--- 18295,18301 ----
     vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1,1,*")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 18243,18248 ****
--- 18313,18319 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
  
***************
*** 18912,18917 ****
--- 18983,18989 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f,*,*")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 19018,19023 ****
--- 19090,19096 ----
    "TARGET_AVX512F"
    "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 19142,19147 ****
--- 19215,19221 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 19239,19244 ****
--- 19313,19319 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 19275,19280 ****
--- 19350,19356 ----
     (set_attr "prefix" "orig,vex,evex")
     (set_attr "prefix_data16" "1,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "mode" "TI")])
  
  (define_expand "one_cmplv1ti2"
***************
*** 20250,20255 ****
--- 20326,20332 ----
  }
    [(set_attr "isa" "noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0,1")
  		      (const_string "gpr16")
***************
*** 20363,20368 ****
--- 20440,20446 ----
      }
  }
    [(set_attr "type" "sselog,ssemov,ssemov")
+    (set_attr "c86_attr" "insertx,*,*")
     (set_attr "length_immediate" "1,0,0")
     (set_attr "prefix" "evex,vex,evex")
     (set_attr "mode" "<sseinsnmode>,<ssequarterinsnmode>,<ssequarterinsnmode>")])
***************
*** 20395,20400 ****
--- 20473,20479 ----
    return "vinsert<shuffletype><extract_suf>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20433,20438 ****
--- 20512,20518 ----
    "TARGET_AVX512DQ"
    "vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20450,20455 ****
--- 20530,20536 ----
    "TARGET_AVX512DQ"
    "vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20465,20470 ****
--- 20546,20552 ----
    "TARGET_AVX512F"
    "vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
***************
*** 20480,20485 ****
--- 20562,20568 ----
    "TARGET_AVX512F"
    "vinsert<shuffletype>64x4\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
***************
*** 20529,20534 ****
--- 20612,20618 ----
    return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "addr" "gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
***************
*** 20592,20597 ****
--- 20676,20682 ----
    return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20628,20633 ****
--- 20713,20719 ----
    return "vshuf<shuffletype>64x2\t{%2, %1, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20691,20696 ****
--- 20777,20783 ----
    return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "addr" "gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
***************
*** 20778,20783 ****
--- 20865,20871 ----
    return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand19>|%0<mask_operand19>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20830,20835 ****
--- 20918,20924 ----
    return "vshuf<shuffletype>32x4\t{%2, %1, %1, %0<mask_operand18>|%0<mask_operand18>, %1, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 21434,21439 ****
--- 21523,21529 ----
    [(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx")
     (set_attr "addr" "*,*,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set (attr "prefix_extra")
       (if_then_else
         (eq (const_string "<MODE>mode") (const_string "V8HImode"))
***************
*** 21455,21460 ****
--- 21545,21551 ----
    "%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set (attr "prefix_extra")
       (if_then_else
         (eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
***************
*** 21475,21480 ****
--- 21566,21572 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 21609,21614 ****
--- 21701,21707 ----
  }
    [(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,*,*,*,*")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 21631,21636 ****
--- 21724,21730 ----
    "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx,avx512dq")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 21703,21708 ****
--- 21797,21806 ----
  	      (const_string "imov")
  	   ]
  	   (const_string "sselog1")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2")
+ 		   (const_string "extr")
+ 		   (const_string "other")))
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 21868,21873 ****
--- 21966,21975 ----
  	      (const_string "mmxmov")
  	   ]
  	   (const_string "sselog")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2,3")
+ 		   (const_string "insr")
+ 		   (const_string "other")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "0,1")
  		   (const_string "gpr16")
***************
*** 22026,22031 ****
--- 22128,22137 ----
         (eq_attr "alternative" "0,1,2,3,4,5")
         (const_string "sselog")
         (const_string "ssemov2")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2,3")
+ 		   (const_string "insr")
+ 		   (const_string "other")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "0,1")
  		   (const_string "gpr16")
***************
*** 22245,22250 ****
--- 22351,22357 ----
     vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "avg")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,<mask_prefix>")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 22273,22278 ****
--- 22380,22386 ----
     vpsadbw\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,maybe_evex")
***************
*** 22287,22292 ****
--- 22395,22401 ----
    "%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 22300,22305 ****
--- 22409,22415 ----
    "%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 22437,22442 ****
--- 22547,22553 ----
    "%vpmovmskb\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22455,22460 ****
--- 22566,22572 ----
    "%vpmovmskb\t{%1, %k0|%k0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22473,22478 ****
--- 22585,22591 ----
    "%vpmovmskb\t{%1, %k0|%k0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22822,22827 ****
--- 22935,22941 ----
    return "%vmaskmovdqu\t{%2, %1|%1, %2}";
  }
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_data16" "1")
     (set (attr "length_address")
       (symbol_ref ("Pmode != word_mode")))
***************
*** 22830,22835 ****
--- 22944,22950 ----
       (symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))")))
     (set_attr "prefix" "maybe_vex")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "TI")])
  
  (define_insn "sse_ldmxcsr"
***************
*** 22922,22927 ****
--- 23037,23043 ----
    "TARGET_AVX2"
    "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 22948,22953 ****
--- 23064,23070 ----
     vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
***************
*** 22989,22994 ****
--- 23106,23112 ----
  }
    [(set_attr "mmx_isa" "native,sse_noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
***************
*** 23012,23017 ****
--- 23130,23136 ----
    "TARGET_AVX2"
    "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 23036,23041 ****
--- 23155,23161 ----
     vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_data16" "1,*")
***************
*** 23076,23081 ****
--- 23196,23202 ----
  }
    [(set_attr "mmx_isa" "native,sse_noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
***************
*** 23132,23137 ****
--- 23253,23259 ----
    "TARGET_AVX2"
    "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
***************
*** 23147,23152 ****
--- 23269,23275 ----
     "TARGET_AVX512BW"
     "vpmaddubsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 23223,23228 ****
--- 23346,23352 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 23259,23264 ****
--- 23383,23389 ----
    [(set_attr "isa" "*,noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
***************
*** 23542,23547 ****
--- 23667,23673 ----
     vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sign")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 23561,23566 ****
--- 23687,23693 ----
    [(set_attr "isa" "*,noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sign")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
     (set_attr "mode" "DI,TI,TI")])
***************
*** 23710,23715 ****
--- 23837,23843 ----
     (set_attr "type" "sselog1")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
+    (set_attr "c86_attr" "abs")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "abs<mode>2_mask"
***************
*** 23722,23727 ****
--- 23850,23856 ----
    "TARGET_AVX512F"
    "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 23735,23740 ****
--- 23864,23870 ----
    "TARGET_AVX512BW"
    "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 23767,23772 ****
--- 23897,23903 ----
    "TARGET_SSE4A"
    "movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "sse4a_vmmovnt<mode>"
***************
*** 23779,23784 ****
--- 23910,23916 ----
    "TARGET_SSE4A"
    "movnt<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_insn "sse4a_extrqi"
***************
*** 23855,23860 ****
--- 23987,23993 ----
     vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
***************
*** 23876,23881 ****
--- 24009,24015 ----
     vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "addr" "gpr16")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
***************
*** 23909,23914 ****
--- 24043,24049 ----
  }
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 24114,24119 ****
--- 24249,24255 ----
     (set_attr "prefix" "orig,orig,vex")
     (set_attr "btver2_decode" "vector,vector,vector")
     (set_attr "znver1_decode" "vector,vector,vector")
+    (set_attr "c86_decode" "vector,vector,vector")
     (set_attr "mode" "<MODE>")])
  
  ;; Mode attribute used by `vmovntdqa' pattern
***************
*** 24129,24134 ****
--- 24265,24271 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 24153,24158 ****
--- 24290,24296 ----
     (set_attr "prefix" "orig,orig,vex")
     (set_attr "btver2_decode" "vector,vector,vector")
     (set_attr "znver1_decode" "vector,vector,vector")
+    (set_attr "c86_decode" "vector,vector,vector")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "avx10_2_mpsadbw<mask_name>"
***************
*** 24212,24217 ****
--- 24350,24356 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "*,*,1")
***************
*** 24353,24358 ****
--- 24492,24498 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24425,24430 ****
--- 24565,24571 ----
    return "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
  }
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24440,24445 ****
--- 24581,24587 ----
    "TARGET_AVX2"
    "vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24466,24471 ****
--- 24608,24614 ----
    "TARGET_AVX2 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24520,24525 ****
--- 24663,24669 ----
    "TARGET_AVX512BW"
    "vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24579,24584 ****
--- 24723,24729 ----
    "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24595,24600 ****
--- 24740,24746 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24741,24746 ****
--- 24887,24893 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24762,24767 ****
--- 24909,24915 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24773,24778 ****
--- 24921,24927 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24850,24855 ****
--- 24999,25005 ----
    "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24863,24868 ****
--- 25013,25019 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24940,24945 ****
--- 25091,25097 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24993,24998 ****
--- 25145,25151 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25052,25057 ****
--- 25205,25211 ----
    "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25065,25070 ****
--- 25219,25225 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25209,25214 ****
--- 25364,25370 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25219,25224 ****
--- 25375,25381 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25292,25297 ****
--- 25449,25455 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25303,25308 ****
--- 25461,25467 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25383,25388 ****
--- 25542,25548 ----
    "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25396,25401 ****
--- 25556,25562 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25445,25450 ****
--- 25606,25612 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25464,25469 ****
--- 25626,25632 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25475,25480 ****
--- 25638,25644 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25547,25552 ****
--- 25711,25717 ----
    "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25560,25565 ****
--- 25725,25731 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25635,25640 ****
--- 25801,25807 ----
    "TARGET_AVX512F"
    "vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25686,25691 ****
--- 25853,25859 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "maybe_evex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "OI")])
***************
*** 25741,25746 ****
--- 25909,25915 ----
    "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25754,25759 ****
--- 25923,25929 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 26206,26211 ****
--- 26376,26382 ----
  }
    [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
     (set_attr "type" "ssecvt")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*,*")
***************
*** 26243,26248 ****
--- 26414,26420 ----
  }
    [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
     (set_attr "type" "ssecvt")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*,*")
***************
*** 26512,26517 ****
--- 26684,26690 ----
    "TARGET_SSE4_2"
    "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 26540,26545 ****
--- 26713,26719 ----
    "TARGET_SSE4_2"
    "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26566,26571 ****
--- 26740,26746 ----
     %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
     %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26643,26648 ****
--- 26818,26824 ----
    "TARGET_SSE4_2"
    "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26667,26672 ****
--- 26843,26849 ----
    "TARGET_SSE4_2"
    "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26691,26696 ****
--- 26868,26874 ----
     %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
     %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26877,26882 ****
--- 27055,27061 ----
    "TARGET_XOP"
    "vphadd<u>bw\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26909,26914 ****
--- 27088,27094 ----
    "TARGET_XOP"
    "vphadd<u>bd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26957,26962 ****
--- 27137,27143 ----
    "TARGET_XOP"
    "vphadd<u>bq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26977,26982 ****
--- 27158,27164 ----
    "TARGET_XOP"
    "vphadd<u>wd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27005,27010 ****
--- 27187,27193 ----
    "TARGET_XOP"
    "vphadd<u>wq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27023,27028 ****
--- 27206,27212 ----
    "TARGET_XOP"
    "vphadd<u>dq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27047,27052 ****
--- 27231,27237 ----
    "TARGET_XOP"
    "vphsubbw\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27067,27072 ****
--- 27252,27258 ----
    "TARGET_XOP"
    "vphsubwd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27085,27090 ****
--- 27271,27277 ----
    "TARGET_XOP"
    "vphsubdq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27791,27796 ****
--- 27978,27984 ----
     vaesenc\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27809,27814 ****
--- 27997,28003 ----
     vaesenclast\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27827,27832 ****
--- 28016,28022 ----
     vaesdec\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27846,27851 ****
--- 28036,28042 ----
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
     (set_attr "btver2_decode" "double,double,double")
***************
*** 27858,27863 ****
--- 28049,28055 ----
    "TARGET_AES"
    "%vaesimc\t{%1, %0|%0, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 27871,27876 ****
--- 28063,28069 ----
    "TARGET_AES"
    "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 27894,27899 ****
--- 28087,28093 ----
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex,evex")
+    (set_attr "c86_decode" "*,vector,vector")
     (set_attr "mode" "TI")])
  
  (define_expand "avx_vzeroall"
***************
*** 28011,28016 ****
--- 28205,28211 ----
    return "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28023,28028 ****
--- 28218,28224 ----
    "TARGET_AVX512VBMI && <mask_mode512bit_condition>"
    "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28035,28040 ****
--- 28231,28237 ----
    "TARGET_AVX512BW && <mask_mode512bit_condition>"
    "vpermw\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28253,28258 ****
--- 28450,28456 ----
    return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28328,28333 ****
--- 28526,28532 ----
    return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28434,28439 ****
--- 28633,28639 ----
     vshuf<shuffletype>32x4\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0}
     vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28446,28451 ****
--- 28646,28652 ----
     vshuf<shuffletype>64x2\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
     vbroadcast<shuffletype>64x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28698,28703 ****
--- 28899,28905 ----
     vinsert<shuffletype>32x4\t{$1, %1, %0, %0|%0, %0, %1, 1}"
    [(set_attr "isa" "noavx512vl,*,*,avx512dq,avx512dq,avx512vl,avx512vl")
     (set_attr "type" "ssemov,sselog1,sselog1,ssemov,sselog1,ssemov,sselog1")
+    (set_attr "c86_attr" "*,insertx,*,*,insertx,*,insertx")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 28756,28761 ****
--- 28958,28964 ----
     vshuf<shuffletype>32x4\t{$0x0, %t1, %t1, %0<mask_operand2>|%0<mask_operand2>, %t1, %t1, 0x0}
     vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28769,28774 ****
--- 28972,28978 ----
     vshuf<shuffletype>32x4\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
     vbroadcast<shuffletype>32x8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "length_immediate" "1,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28786,28791 ****
--- 28990,28996 ----
     vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
     vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28883,28888 ****
--- 29088,29094 ----
    "TARGET_AVX512F"
    "vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28899,28904 ****
--- 29105,29111 ----
    "TARGET_AVX512F"
    "vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28928,28933 ****
--- 29135,29141 ----
     vpermt2<ssemodesuffix>\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}
     vpermi2<ssemodesuffix>\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28959,28964 ****
--- 29167,29173 ----
    "TARGET_AVX512F"
    "vpermt2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 29037,29042 ****
--- 29246,29252 ----
    return "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 29144,29149 ****
--- 29354,29360 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 29168,29173 ****
--- 29379,29385 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 29191,29196 ****
--- 29403,29409 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 29214,29219 ****
--- 29427,29433 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 29236,29241 ****
--- 29450,29456 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 29258,29263 ****
--- 29473,29479 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 29283,29288 ****
--- 29499,29505 ----
     vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 29310,29315 ****
--- 29527,29533 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 29329,29334 ****
--- 29547,29553 ----
      return "vmaskmov<ssefltmodesuffix>\t{%1, %2, %0|%0, %2, %1}";
  }
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 29350,29355 ****
--- 29569,29575 ----
      return "vmaskmov<ssefltmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
  }
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 29745,29750 ****
--- 29965,29971 ----
    [(set_attr "isa" "noavx512f,avx512f,*,*")
     (set_attr "addr" "gpr16,*,*,*")
     (set_attr "type" "sselog,sselog,ssemov,ssemov")
+    (set_attr "c86_attr" "insertx,insertx,*,*")
     (set_attr "prefix_extra" "1,1,*,*")
     (set_attr "length_immediate" "1,1,*,*")
     (set_attr "prefix" "maybe_evex")
***************
*** 30355,30360 ****
--- 30576,30582 ----
    "TARGET_AVX512F"
    "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30368,30373 ****
--- 30590,30596 ----
    "TARGET_AVX512VBMI2"
    "vpcompress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30381,30386 ****
--- 30604,30610 ----
    "TARGET_AVX512F"
    "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "memory" "store")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30395,30400 ****
--- 30619,30625 ----
    "TARGET_AVX512VBMI2"
    "vpcompress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "memory" "store")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30419,30424 ****
--- 30644,30650 ----
    "TARGET_AVX512F"
    "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "expand")
     (set_attr "prefix" "evex")
     (set_attr "memory" "none,load")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30433,30438 ****
--- 30659,30665 ----
    "TARGET_AVX512VBMI2"
    "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "expand")
     (set_attr "prefix" "evex")
     (set_attr "memory" "none,load")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30625,30630 ****
--- 30852,30858 ----
     "TARGET_AVX512BW"
    "vdbpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30636,30641 ****
--- 30864,30870 ----
    "TARGET_AVX512CD"
    "vplzcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30648,30653 ****
--- 30877,30883 ----
    "vpconflict<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
     (set_attr "prefix" "evex")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "sha1msg1"
***************
*** 30910,30915 ****
--- 31140,31146 ----
    "TARGET_AVX512IFMA"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 30926,30931 ****
--- 31157,31163 ----
    vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "isa" "avxifma,avx512ifmavl")
     (set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix" "vex,evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30943,30948 ****
--- 31175,31181 ----
    "TARGET_AVX512IFMA"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30959,30964 ****
--- 31192,31198 ----
    "TARGET_AVX512IFMA"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 31562,31567 ****
--- 31796,31802 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31580,31585 ****
--- 31815,31821 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31598,31603 ****
--- 31834,31840 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31616,31621 ****
--- 31853,31859 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
diff -Nrcpad gcc-16-20260606/gcc/config/i386/x86-tune-costs.h gcc-16-20260613/gcc/config/i386/x86-tune-costs.h
*** gcc-16-20260606/gcc/config/i386/x86-tune-costs.h	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/x86-tune-costs.h	Sat Jun 13 22:32:06 2026
*************** struct processor_costs core_cost = {
*** 4420,4422 ****
--- 4420,4722 ----
    COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
  };
  
+ /*  C86_4G_M4 has optimized REP instruction for medium sized blocks, but for
+     very small blocks it is better to use loop.  For large blocks, libcall
+     can do nontemporary accesses and beat inline considerably.  */
+ static stringop_algs c86_4g_m4_memcpy[2] = {
+   /* 32-bit tuning.  */
+   {libcall, {{6, loop, false},
+ 	     {14, unrolled_loop, false},
+ 	     {-1, libcall, false}}},
+   /* 64-bit tuning.  */
+   {libcall, {{16, loop, false},
+ 	     {128, rep_prefix_8_byte, false},
+ 	     {-1, libcall, false}}}};
+ static stringop_algs c86_4g_m4_memset[2] = {
+   /* 32-bit tuning.  */
+   {libcall, {{8, loop, false},
+ 	     {24, unrolled_loop, false},
+ 	     {128, rep_prefix_4_byte, false},
+ 	     {-1, libcall, false}}},
+   /* 64-bit tuning.  */
+   {libcall, {{48, unrolled_loop, false},
+ 	     {128, rep_prefix_8_byte, false},
+ 	     {-1, libcall, false}}}};
+ static const
+ struct processor_costs c86_4g_m4_cost = {
+   {
+   /* Start of register allocator costs.  integer->integer move cost is 2.  */
+ 
+   /* reg-reg moves are done by renaming and thus they are even cheaper than
+      1 cycle.  Because reg-reg move cost is 2 and the following tables
+      correspond to doubles of latencies, we do not model this correctly.
+      It does not seem to make practical difference to bump prices up even
+      more.  */
+   6,					/* cost for loading QImode using
+ 					   movzbl.  */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   2,					/* cost of reg,reg fld/fst.  */
+   {6, 6, 16},				/* cost of loading fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   {8, 8, 16},				/* cost of storing fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   2,					/* cost of moving MMX register.  */
+   {6, 6},				/* cost of loading MMX registers
+ 					   in SImode and DImode.  */
+   {8, 8},				/* cost of storing MMX registers
+ 					   in SImode and DImode.  */
+   2, 3, 6,				/* cost of moving XMM,YMM,ZMM register.  */
+   {6, 6, 6, 12, 24},			/* cost of loading SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   {8, 8, 8, 16, 32},			/* cost of storing SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   6, 6,				/* SSE->integer and integer->SSE moves.  */
+   8, 8,				/* mask->integer and integer->mask moves */
+   {6, 6, 6},				/* cost of loading mask register
+ 					   in QImode, HImode, SImode.  */
+   {8, 8, 8},				/* cost if storing mask register
+ 					   in QImode, HImode, SImode.  */
+   2,					/* cost of moving mask register.  */
+   /* End of register allocator costs.  */
+   },
+ 
+   COSTS_N_INSNS (1),			/* cost of an add instruction.  */
+   COSTS_N_INSNS (1),			/* cost of a lea instruction.  */
+   COSTS_N_INSNS (1),			/* variable shift costs.  */
+   COSTS_N_INSNS (1),			/* constant shift costs.  */
+   {COSTS_N_INSNS (3),			/* cost of starting multiply for QI.  */
+    COSTS_N_INSNS (3),			/*				 HI.  */
+    COSTS_N_INSNS (3),			/*				 SI.  */
+    COSTS_N_INSNS (3),			/*				 DI.  */
+    COSTS_N_INSNS (3)},			/*			      other.  */
+   0,					/* cost of multiply per each bit
+ 					    set.  */
+    /* Depending on parameters, idiv can get faster on HYGON.  This is upper
+       bound.  */
+   {COSTS_N_INSNS (16),			/* cost of a divide/mod for QI.  */
+    COSTS_N_INSNS (22),			/*			    HI.  */
+    COSTS_N_INSNS (30),			/*			    SI.  */
+    COSTS_N_INSNS (45),			/*			    DI.  */
+    COSTS_N_INSNS (45)},			/*			    other.  */
+   COSTS_N_INSNS (1),			/* cost of movsx.  */
+   COSTS_N_INSNS (1),			/* cost of movzx.  */
+   8,					/* "large" insn.  */
+   9,					/* MOVE_RATIO.  */
+   6,					/* CLEAR_RATIO */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   {6, 6, 6, 12, 24},			/* cost of loading SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {8, 8, 8, 16, 32},			/* cost of storing SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {6, 6, 6, 12, 24},			/* cost of unaligned loads.  */
+   {8, 8, 8, 16, 32},			/* cost of unaligned stores.  */
+   2, 3, 6,				/* cost of moving XMM,YMM,ZMM register.  */
+   6,					/* cost of moving SSE register to integer.  */
+   6,					/* cost of moving integer register to SSE.  */
+ 
+   18, 8,				/* Gather load static, per_elt.  */
+   18, 10,				/* Gather store static, per_elt.  */
+   32,					/* size of l1 cache.  */
+   512,					/* size of l2 cache.  */
+   64,					/* size of prefetch block.  */
+   /* C86_4G_M4 processors never drop prefetches; if they cannot be performed
+      immediately, they are queued.  We set number of simultaneous prefetches
+      to a large constant to reflect this (it probably is not a good idea not
+      to limit number of prefetches at all, as their execution also takes some
+      time).  */
+   100,					/* number of parallel prefetches.  */
+   3,					/* Branch cost.  */
+   COSTS_N_INSNS (5),			/* cost of FADD and FSUB insns.  */
+   COSTS_N_INSNS (5),			/* cost of FMUL instruction.  */
+ 
+   COSTS_N_INSNS (15),			/* cost of FDIV instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FABS instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FCHS instruction.  */
+ 
+   COSTS_N_INSNS (10),			/* cost of FSQRT instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of cheap SSE instruction.  */
+   COSTS_N_INSNS (3),			/* cost of ADDSS/SD SUBSS/SD insns.  */
+   COSTS_N_INSNS (3),			/* cost of MULSS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of MULSD instruction.  */
+   COSTS_N_INSNS (5),			/* cost of FMA SS instruction.  */
+   COSTS_N_INSNS (5),			/* cost of FMA SD instruction.  */
+   COSTS_N_INSNS (10),			/* cost of DIVSS instruction.  */
+ 
+   COSTS_N_INSNS (13),			/* cost of DIVSD instruction.  */
+   COSTS_N_INSNS (10),			/* cost of SQRTSS instruction.  */
+   COSTS_N_INSNS (15),			/* cost of SQRTSD instruction.  */
+ 
+   COSTS_N_INSNS (4),			/* cost of CVTSS2SD etc.  */
+   COSTS_N_INSNS (5),			/* cost of 256bit VCVTPS2PD etc.  */
+   COSTS_N_INSNS (10),			/* cost of 512bit VCVTPS2PD etc.  */
+   COSTS_N_INSNS (5),			/* cost of CVTSI2SS instruction.  */
+   COSTS_N_INSNS (5),			/* cost of CVT(T)SS2SI instruction.  */
+   COSTS_N_INSNS (5),			/* cost of CVTPI2PS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of CVT(T)PS2PI instruction.  */
+ 
+   4, 4, 3, 6,				/* reassoc int, fp, vec_int, vec_fp.  */
+   {8, 1, 6},				/* latency times throughput of
+ 					   FMA/DOT_PROD_EXPR/SAD_EXPR,
+ 					   it's used to determine unroll
+ 					   factor in the vectorizer.  */
+   4,					/* Limit how much the autovectorizer
+ 					   may unroll a loop.  */
+   c86_4g_m4_memcpy,
+   c86_4g_m4_memset,
+   COSTS_N_INSNS (4),			/* cond_taken_branch_cost.  */
+   COSTS_N_INSNS (2),			/* cond_not_taken_branch_cost.  */
+   "16",					/* Loop alignment.  */
+   "16",					/* Jump alignment.  */
+   "0:0:8",				/* Label alignment.  */
+   "16",					/* Func alignment.  */
+   4,					/* Small unroll limit.  */
+   2,					/* Small unroll factor.  */
+   COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
+ };
+ 
+ struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost;
+ 
+ struct processor_costs c86_4g_m7_cost = {
+   {
+   /* Start of register allocator costs.  integer->integer move cost is 2.  */
+ 
+   /* reg-reg moves are done by renaming and thus they are even cheaper than
+      1 cycle.  Because reg-reg move cost is 2 and following tables correspond
+      to doubles of latencies, we do not model this correctly.  It does not
+      seem to make practical difference to bump prices up even more.  */
+   6,					/* cost for loading QImode using
+ 					   movzbl.  */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   2,					/* cost of reg,reg fld/fst.  */
+   {14, 14, 17},				/* cost of loading fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   {12, 12, 16},				/* cost of storing fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   2,					/* cost of moving MMX register.  */
+   {6, 6},				/* cost of loading MMX registers
+ 					   in SImode and DImode.  */
+   {8, 8},				/* cost of storing MMX registers
+ 					   in SImode and DImode.  */
+   2, 2, 3,				/* cost of moving XMM,YMM,ZMM
+ 					   register.  */
+   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   {8, 8, 8, 12, 12},			/* cost of storing SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   6, 8,					/* SSE->integer and integer->SSE
+ 					   moves.  */
+   8, 8,					/* mask->integer and integer->mask moves */
+   {6, 6, 6},				/* cost of loading mask register
+ 					   in QImode, HImode, SImode.  */
+   {8, 8, 8},				/* cost if storing mask register
+ 					   in QImode, HImode, SImode.  */
+   2,					/* cost of moving mask register.  */
+   /* End of register allocator costs.  */
+   },
+ 
+   COSTS_N_INSNS (1),			/* cost of an add instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of a lea instruction.  */
+   COSTS_N_INSNS (1),			/* variable shift costs.  */
+   COSTS_N_INSNS (1),			/* constant shift costs.  */
+   {COSTS_N_INSNS (3),			/* cost of starting multiply for QI.  */
+    COSTS_N_INSNS (3),			/* 				 HI.  */
+    COSTS_N_INSNS (3),			/*				 SI.  */
+    COSTS_N_INSNS (3),			/*				 DI.  */
+    COSTS_N_INSNS (3)},			/*			other.  */
+   0,					/* cost of multiply per each bit
+ 					   set.  */
+   {COSTS_N_INSNS (15),			/* cost of a divide/mod for QI.  */
+    COSTS_N_INSNS (17),			/* 			    HI.  */
+    COSTS_N_INSNS (25),			/*			    SI.  */
+    COSTS_N_INSNS (41),			/*			    DI.  */
+    COSTS_N_INSNS (41)},			/*			    other.  */
+   COSTS_N_INSNS (1),			/* cost of movsx.  */
+   COSTS_N_INSNS (1),			/* cost of movzx.  */
+   8,					/* "large" insn.  */
+   9,					/* MOVE_RATIO.  */
+   6,					/* CLEAR_RATIO */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {8, 8, 8, 12, 12},			/* cost of storing SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {6, 6, 10, 10, 12},			/* cost of unaligned loads.  */
+   {8, 8, 8, 12, 12},			/* cost of unaligned stores.  */
+   2, 2, 3,				/* cost of moving XMM,YMM,ZMM
+ 					   register.  */
+   6,					/* cost of moving SSE register to integer.  */
+   6,					/* cost of moving integer register to SSE.  */
+ 
+   14, 10,				/* Gather load static, per_elt.  */
+   14, 20,				/* Gather store static, per_elt.  */
+   32,					/* size of l1 cache.  */
+   512,					/* size of l2 cache.  */
+   64,					/* size of prefetch block.  */
+ 
+   100,					/* number of parallel prefetches.  */
+   3,					/* Branch cost.  */
+   COSTS_N_INSNS (5),			/* cost of FADD and FSUB insns.  */
+   COSTS_N_INSNS (5),			/* cost of FMUL instruction.  */
+ 
+   COSTS_N_INSNS (15),			/* cost of FDIV instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FABS instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FCHS instruction.  */
+ 
+   COSTS_N_INSNS (22),			/* cost of FSQRT instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of cheap SSE instruction.  */
+   COSTS_N_INSNS (3),			/* cost of ADDSS/SD SUBSS/SD insns.  */
+   COSTS_N_INSNS (3),			/* cost of MULSS instruction.  */
+   COSTS_N_INSNS (3),			/* cost of MULSD instruction.  */
+   COSTS_N_INSNS (4),			/* cost of FMA SS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of FMA SD instruction.  */
+   COSTS_N_INSNS (13),			/* cost of DIVSS instruction.  */
+ 
+   COSTS_N_INSNS (10),			/* cost of DIVSD instruction.  */
+   COSTS_N_INSNS (14),			/* cost of SQRTSS instruction.  */
+   COSTS_N_INSNS (20),			/* cost of SQRTSD instruction.  */
+ 
+   COSTS_N_INSNS (4),			/* cost of CVTSS2SD etc.  */
+   COSTS_N_INSNS (5),			/* cost of 256bit VCVTPS2PD etc.  */
+   COSTS_N_INSNS (10),			/* cost of 512bit VCVTPS2PD etc.  */
+   COSTS_N_INSNS (5),			/* cost of CVTSI2SS instruction.  */
+   COSTS_N_INSNS (5),			/* cost of CVT(T)SS2SI instruction.  */
+   COSTS_N_INSNS (5),			/* cost of CVTPI2PS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of CVT(T)PS2PI instruction.  */
+   4, 4, 3, 6,				/* reassoc int, fp, vec_int, vec_fp.  */
+   {8, 8, 6},				/* latency times throughput of
+ 					   FMA/DOT_PROD_EXPR/SAD_EXPR,
+ 					   it's used to determine unroll
+ 					   factor in the vectorizer.  */
+   4,					/* Limit how much the autovectorizer
+ 					   may unroll a loop.  */
+   c86_4g_m4_memcpy,
+   c86_4g_m4_memset,
+   COSTS_N_INSNS (4),			/* cond_taken_branch_cost.  */
+   COSTS_N_INSNS (2),			/* cond_not_taken_branch_cost.  */
+   "16",					/* Loop alignment.  */
+   "16",					/* Jump alignment.  */
+   "0:0:8",				/* Label alignment.  */
+   "16",					/* Func alignment.  */
+   4,					/* Small unroll limit.  */
+   2,					/* Small unroll factor.  */
+   COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
+ };
diff -Nrcpad gcc-16-20260606/gcc/config/i386/x86-tune-sched.cc gcc-16-20260613/gcc/config/i386/x86-tune-sched.cc
*** gcc-16-20260606/gcc/config/i386/x86-tune-sched.cc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/x86-tune-sched.cc	Sat Jun 13 22:32:06 2026
*************** ix86_issue_rate (void)
*** 91,96 ****
--- 91,99 ----
         is limits of the decoders.  */
      case PROCESSOR_ZNVER5:
      case PROCESSOR_ZNVER6:
+     case PROCESSOR_C86_4G_M4:
+     case PROCESSOR_C86_4G_M6:
+     case PROCESSOR_C86_4G_M7:
        return 4;
  
      case PROCESSOR_ICELAKE_CLIENT:
*************** ix86_adjust_cost (rtx_insn *insn, int de
*** 440,445 ****
--- 443,451 ----
      case PROCESSOR_ZNVER4:
      case PROCESSOR_ZNVER5:
      case PROCESSOR_ZNVER6:
+     case PROCESSOR_C86_4G_M4:
+     case PROCESSOR_C86_4G_M6:
+     case PROCESSOR_C86_4G_M7:
        /* Stack engine allows to execute push&pop instructions in parall.  */
        if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
  	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
diff -Nrcpad gcc-16-20260606/gcc/config/i386/x86-tune.def gcc-16-20260613/gcc/config/i386/x86-tune.def
*** gcc-16-20260606/gcc/config/i386/x86-tune.def	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/i386/x86-tune.def	Sat Jun 13 22:32:06 2026
*************** see the files COPYING3 and COPYING.RUNTI
*** 42,48 ****
  DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
            m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
! 	  | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
  	  | m_GENERIC)
  
  /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
--- 42,48 ----
  DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
            m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
! 	  | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
  	  | m_GENERIC)
  
  /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
*************** DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENC
*** 53,59 ****
            m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
     destinations to be 128bit to allow register renaming on 128bit SSE units,
--- 53,59 ----
            m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
     destinations to be 128bit to allow register renaming on 128bit SSE units,
*************** DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENC
*** 64,70 ****
  DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
            m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
     partial write to the destination in scalar SSE conversion from FP
--- 64,70 ----
  DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
            m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
     partial write to the destination in scalar SSE conversion from FP
*************** DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CO
*** 73,79 ****
  	  "sse_partial_reg_fp_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
     write to the destination in scalar SSE conversion from integer to FP.  */
--- 73,79 ----
  	  "sse_partial_reg_fp_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
     write to the destination in scalar SSE conversion from integer to FP.  */
*************** DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVE
*** 81,87 ****
  	  "sse_partial_reg_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_GENERIC)
  
  /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
     several insns to break false dependency on the dest register for GLC
--- 81,87 ----
  	  "sse_partial_reg_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
     several insns to break false dependency on the dest register for GLC
*************** DEF_TUNE (X86_TUNE_MOVX, "movx",
*** 113,144 ****
            m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
  	  | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
     full sized loads.  */
  DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
            m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
     conditional jump instruction for 32 bit TARGET.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
! 	  m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
     conditional jump instruction for TARGET_64BIT.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
     subsequent conditional jump instruction when the condition jump
     check sign flag (SF) or overflow flag (OF).  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
     jump instruction when the alu instruction produces the CCFLAG consumed by
--- 113,145 ----
            m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
  	  | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
     full sized loads.  */
  DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
            m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
     conditional jump instruction for 32 bit TARGET.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
! 	  m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
     conditional jump instruction for TARGET_64BIT.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
     subsequent conditional jump instruction when the condition jump
     check sign flag (SF) or overflow flag (OF).  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
     jump instruction when the alu instruction produces the CCFLAG consumed by
*************** DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE,
*** 201,214 ****
  /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
  DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
  	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
     Some chips, like 486 and Pentium works faster with separate load
     and push instructions.  */
  DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
            m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
     over esp subtraction.  */
--- 202,216 ----
  /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
  DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
  	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
     Some chips, like 486 and Pentium works faster with separate load
     and push instructions.  */
  DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
            m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
! 	  | m_GENERIC)
  
  /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
     over esp subtraction.  */
*************** DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES,
*** 292,298 ****
            ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	    | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_GENERIC))
  
  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
--- 294,300 ----
            ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	    | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_C86_4G | m_GENERIC))
  
  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
*************** DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVS
*** 339,352 ****
  DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
  	  "misaligned_move_string_pro_epilogues",
  	  m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
  DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
  	  | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
  DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
--- 341,354 ----
  DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
  	  "misaligned_move_string_pro_epilogues",
  	  m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
  DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
  	  | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
  DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
*************** DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
*** 357,363 ****
  DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
  	  m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
     for bit-manipulation instructions.  */
--- 359,365 ----
  DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
  	  m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
     for bit-manipulation instructions.  */
*************** DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "on
*** 391,397 ****
  /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
  DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
  	 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	 | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
     generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
--- 393,399 ----
  /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
  DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
  	 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	 | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
     generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
*************** DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use
*** 419,428 ****
            ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
  	    | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_GENERIC))
  
  /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
! DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN)
  
  /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
  DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
--- 421,431 ----
            ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
  	    | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_C86_4G | m_GENERIC))
  
  /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
! DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_C86_4G)
  
  /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
  DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
*************** DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OP
*** 446,475 ****
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
  	  | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
! 	  | m_GENERIC)
  
  /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
     instead of a sequence loading registers by parts.  */
  DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
  	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
     precision 128bit instructions instead of double where possible.   */
  DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
! 	  m_BDVER | m_ZNVER)
  
  /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
  DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
  	  m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
     xorps/xorpd and other variants.  */
  DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
     to SSE registers.  If disabled, the moves will be done by storing
--- 449,479 ----
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
  	  | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
     instead of a sequence loading registers by parts.  */
  DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
  	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
     precision 128bit instructions instead of double where possible.   */
  DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
! 	  m_BDVER | m_ZNVER | m_C86_4G)
  
  /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
  DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
  	  m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
     xorps/xorpd and other variants.  */
  DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
     to SSE registers.  If disabled, the moves will be done by storing
*************** DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES,
*** 535,580 ****
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
!           | m_YONGFENG | m_SHIJIDADAO | m_GENERIC)
  
  /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
  	  m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5  | m_ZNVER6 | m_CORE_HYBRID
  	  | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
     smaller FMA chain.  */
--- 539,587 ----
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
! 	    | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
! 
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
! 	    | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
! 	  | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_C86_4G)
  
  /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
  	  m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5  | m_ZNVER6 | m_CORE_HYBRID
  	  | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC | m_C86_4G)
  
  /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
     smaller FMA chain.  */
*************** DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV,
*** 597,603 ****
  /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
     V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
  DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
!    "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5)
  
  /*****************************************************************************/
  /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
--- 604,610 ----
  /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
     V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
  DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
!    "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
  
  /*****************************************************************************/
  /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 632,650 ****
  	 "avx256_avoid_vec_perm", m_CORE_ATOM)
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
! DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
  
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
--- 639,659 ----
  	 "avx256_avoid_vec_perm", m_CORE_ATOM)
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
! DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4
! 	  | m_C86_4G_M7)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3
! 	  | m_C86_4G_M4 | m_C86_4G_M6)
  
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
*************** DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES,
*** 654,660 ****
  /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
     when fit.  */
  DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
! 	  m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
  
  /*****************************************************************************/
  /*****************************************************************************/
--- 663,669 ----
  /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
     when fit.  */
  DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
! 	  m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)
  
  /*****************************************************************************/
  /*****************************************************************************/
*************** DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "pro
*** 796,799 ****
  DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
  
  /* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd.  */
! DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE)
--- 805,808 ----
  DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
  
  /* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd.  */
! DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE | m_C86_4G)
diff -Nrcpad gcc-16-20260606/gcc/config/mips/sync.md gcc-16-20260613/gcc/config/mips/sync.md
*** gcc-16-20260606/gcc/config/mips/sync.md	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config/mips/sync.md	Sat Jun 13 22:32:06 2026
***************
*** 179,185 ****
  	(unspec_volatile:SI
            [(match_operand:SI 2 "register_operand" "d")
  	   (match_operand:SI 3 "register_operand" "d")
! 	   (atomic_hiqi_op:SI (match_dup 0)
  			      (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
  	  UNSPEC_SYNC_OLD_OP_12))
     (clobber (match_scratch:SI 5 "=&d"))]
--- 179,185 ----
  	(unspec_volatile:SI
            [(match_operand:SI 2 "register_operand" "d")
  	   (match_operand:SI 3 "register_operand" "d")
! 	   (atomic_hiqi_op:SI (match_dup 1)
  			      (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
  	  UNSPEC_SYNC_OLD_OP_12))
     (clobber (match_scratch:SI 5 "=&d"))]
***************
*** 220,226 ****
            [(match_operand:SI 1 "memory_operand" "+ZC")
  	   (match_operand:SI 2 "register_operand" "d")
  	   (match_operand:SI 3 "register_operand" "d")
! 	   (atomic_hiqi_op:SI (match_dup 0)
  			      (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
  	  UNSPEC_SYNC_NEW_OP_12))
     (set (match_dup 1)
--- 220,226 ----
            [(match_operand:SI 1 "memory_operand" "+ZC")
  	   (match_operand:SI 2 "register_operand" "d")
  	   (match_operand:SI 3 "register_operand" "d")
! 	   (atomic_hiqi_op:SI (match_dup 1)
  			      (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
  	  UNSPEC_SYNC_NEW_OP_12))
     (set (match_dup 1)
***************
*** 228,234 ****
  	  [(match_dup 1)
  	   (match_dup 2)
  	   (match_dup 3)
! 	   (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
    "GENERATE_LL_SC"
    { return mips_output_sync_loop (insn, operands); }
    [(set_attr "sync_insn1" "<insn>")
--- 228,235 ----
  	  [(match_dup 1)
  	   (match_dup 2)
  	   (match_dup 3)
! 	   (atomic_hiqi_op:SI (match_dup 1) (match_dup 4))]
! 	  UNSPEC_SYNC_NEW_OP_12))]
    "GENERATE_LL_SC"
    { return mips_output_sync_loop (insn, operands); }
    [(set_attr "sync_insn1" "<insn>")
diff -Nrcpad gcc-16-20260606/gcc/config.gcc gcc-16-20260613/gcc/config.gcc
*** gcc-16-20260606/gcc/config.gcc	Sat Jun  6 22:32:05 2026
--- gcc-16-20260613/gcc/config.gcc	Sat Jun 13 22:32:06 2026
*************** sapphirerapids alderlake rocketlake eden
*** 768,774 ****
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
  arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
! native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
--- 768,774 ----
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
  arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
! c86-4g-m4 c86-4g-m6 c86-4g-m7 native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
*************** case ${target} in
*** 4006,4011 ****
--- 4006,4023 ----
  	cpu=pentiumpro
  	arch_without_sse2=yes
  	;;
+       c86_4g_m4-*)
+ 	arch=c86-4g-m4
+ 	cpu=c86-4g-m4
+ 	;;
+       c86_4g_m6-*)
+ 	arch=c86-4g-m6
+ 	cpu=c86-4g-m6
+ 	;;
+       c86_4g_m7-*)
+ 	arch=c86-4g-m7
+ 	cpu=c86-4g-m7
+ 	;;
        *)
  	arch=pentiumpro
  	cpu=generic
*************** case ${target} in
*** 4108,4113 ****
--- 4120,4137 ----
  	arch=corei7
  	cpu=corei7
  	;;
+       c86_4g_m4-*)
+ 	arch=c86-4g-m4
+ 	cpu=c86-4g-m4
+ 	;;
+       c86_4g_m6-*)
+ 	arch=c86-4g-m6
+ 	cpu=c86-4g-m6
+ 	;;
+       c86_4g_m7-*)
+ 	arch=c86-4g-m7
+ 	cpu=c86-4g-m7
+ 	;;
        *)
  	arch=x86-64
  	cpu=generic
diff -Nrcpad gcc-16-20260606/gcc/cp/ChangeLog gcc-16-20260613/gcc/cp/ChangeLog
*** gcc-16-20260606/gcc/cp/ChangeLog	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/cp/ChangeLog	Sat Jun 13 22:32:06 2026
***************
*** 1,3 ****
--- 1,66 ----
+ 2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-21  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/125284
+ 	PR c++/125333
+ 	* pt.cc (tsubst_decl) <case USING_DECL>: Copy targs before
+ 	modifying them.
+ 
+ 2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/125498
+ 	* mangle.cc (write_reflection): Use DECL_PARM_INDEX for
+ 	computing the parameter index.
+ 
+ 2026-06-05  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-05  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/125334
+ 	* module.cc (depset::hash::add_dependent_adl_entities):
+ 	Disable when inside a header unit.
+ 
+ 2026-06-05  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-05  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* module.cc (dep_adl_info::args): Initializer to nullptr
+ 	instead of immediately allocating.
+ 	(depset::hash::add_dependent_adl_entities): Exit early
+ 	for non-type-dependent calls and operator expressions.
+ 	Only allocate dep_adl_info::args if we're not exiting early.
+ 	Correct all-type-dependent args test.
+ 	* name-lookup.cc (name_lookup::preserve_state): Replace
+ 	propagation of tentative flag with assert that it's not
+ 	set.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-03  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/125378
+ 	* tree.cc (build_min_non_dep_op_overload): Handle comparison
+ 	operator expressions rewritten from a <=> that contain an
+ 	integer promotion.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-03  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/125490
+ 	* parser.cc (cp_parser_constraint_expression): Pass
+ 	no_toplevel_fold_p=false instead of =true to
+ 	cp_parser_binary_expression.
+ 
  2026-06-01  Jakub Jelinek  <jakub@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260606/gcc/cp/mangle.cc gcc-16-20260613/gcc/cp/mangle.cc
*** gcc-16-20260606/gcc/cp/mangle.cc	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/cp/mangle.cc	Sat Jun 13 22:32:06 2026
*************** write_reflection (tree refl)
*** 4220,4232 ****
    else if (strcmp (prefix, "pa") == 0)
      {
        tree fn = DECL_CONTEXT (arg);
!       tree args = FUNCTION_FIRST_USER_PARM (fn);
!       int idx = 0;
!       while (arg != args)
! 	{
! 	  args = DECL_CHAIN (args);
! 	  ++idx;
! 	}
        write_compact_number (idx);
        write_encoding (fn);
      }
--- 4220,4227 ----
    else if (strcmp (prefix, "pa") == 0)
      {
        tree fn = DECL_CONTEXT (arg);
!       /* DECL_PARM_INDEX is 1-based but here we want a 0-based index.  */
!       const int idx = DECL_PARM_INDEX (arg) - 1;
        write_compact_number (idx);
        write_encoding (fn);
      }
diff -Nrcpad gcc-16-20260606/gcc/cp/pt.cc gcc-16-20260613/gcc/cp/pt.cc
*** gcc-16-20260606/gcc/cp/pt.cc	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/cp/pt.cc	Sat Jun 13 22:32:06 2026
*************** tsubst_decl (tree t, tree args, tsubst_f
*** 16086,16091 ****
--- 16086,16092 ----
  		  r = error_mark_node;
  		  break;
  		}
+ 	      name = copy_node (name);
  	      for (tree& elt : tree_vec_range (name))
  		elt = make_conv_op_name (elt);
  	      variadic_p = true;
diff -Nrcpad gcc-16-20260606/gcc/doc/extend.texi gcc-16-20260613/gcc/doc/extend.texi
*** gcc-16-20260606/gcc/doc/extend.texi	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/doc/extend.texi	Sat Jun 13 22:32:07 2026
*************** AMD Family 1ah Zen version 5.
*** 29051,29056 ****
--- 29051,29068 ----
  
  @item znver6
  AMD Family 1ah Zen version 6.
+ 
+ @item hygonfam18h
+ HYGON Family 18h CPU.
+ 
+ @item c86-4g-m4
+ HYGON Family 18h model 4 dharma CPU.
+ 
+ @item c86-4g-m6
+ HYGON Family 18h model 6 shanghai CPU.
+ 
+ @item c86-4g-m7
+ HYGON Family 18h model 7 chengdu CPU.
  @end table
  
  Here is an example:
diff -Nrcpad gcc-16-20260606/gcc/doc/invoke.texi gcc-16-20260613/gcc/doc/invoke.texi
*** gcc-16-20260606/gcc/doc/invoke.texi	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/doc/invoke.texi	Sat Jun 13 22:32:07 2026
*************** instruction set support.
*** 35391,35396 ****
--- 35391,35417 ----
  
  @item geode
  AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
+ 
+ @item c86-4g-m4
+ HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+ 
+ @item c86-4g-m6
+ HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+ 
+ @item c86-4g-m7
+ HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
+ AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,
+ AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,
+ WBNOINVD instruction set support.
  @end table
  
  @opindex mtune
diff -Nrcpad gcc-16-20260606/gcc/doc/sourcebuild.texi gcc-16-20260613/gcc/doc/sourcebuild.texi
*** gcc-16-20260606/gcc/doc/sourcebuild.texi	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/doc/sourcebuild.texi	Sat Jun 13 22:32:07 2026
*************** ARM target supporting @code{-mbranch-pro
*** 2351,2356 ****
--- 2351,2361 ----
  @item arm_pacbti_hw
  Test system supports for executing non nop pacbti instructions.
  
+ @item arm_mixed_fp
+ On Arm targets, true when the target uses hardware instructions for
+ single-precision floatint-point values, but software emulation for
+ double-precision values.
+ 
  @end table
  
  @subsubsection AArch64-specific attributes
diff -Nrcpad gcc-16-20260606/gcc/fortran/ChangeLog gcc-16-20260613/gcc/fortran/ChangeLog
*** gcc-16-20260606/gcc/fortran/ChangeLog	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/fortran/ChangeLog	Sat Jun 13 22:32:07 2026
***************
*** 1,3 ****
--- 1,24 ----
+ 2026-06-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/125669
+ 	* decl.cc (gfc_get_pdt_instance): If the bound expressions for
+ 	and array component, of the length expression for a character
+ 	component, gave simplified to a constant, do not set attributes
+ 	pdt_array and pdt_string respectively.
+ 
+ 2026-06-08  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2026-06-06  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/125606
+ 	* trans-intrinsic.cc (gfc_conv_intrinsic_loc): When the argument
+ 	of LOC() is not scalar or known to be simply contiguous, simply
+ 	take the address of the argument array's first element.
+ 
  2026-06-01  Harald Anlauf  <anlauf@gmx.de>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260606/gcc/fortran/decl.cc gcc-16-20260613/gcc/fortran/decl.cc
*** gcc-16-20260606/gcc/fortran/decl.cc	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/fortran/decl.cc	Sat Jun 13 22:32:07 2026
*************** gfc_get_pdt_instance (gfc_actual_arglist
*** 4472,4477 ****
--- 4472,4478 ----
        if (c1->as && c1->as->type == AS_EXPLICIT)
  	{
  	  bool pdt_array = false;
+ 	  bool all_constant = true;
  
  	  /* Are the bounds of the array parameterized?  */
  	  for (i = 0; i < c1->as->rank; i++)
*************** gfc_get_pdt_instance (gfc_actual_arglist
*** 4494,4508 ****
  		gfc_replace_expr (c2->as->lower[i], e);
  	      else
  		gfc_free_expr (e);
  	      e = gfc_copy_expr (c1->as->upper[i]);
  	      gfc_insert_kind_parameter_exprs (e);
  	      if (gfc_simplify_expr (e, 1))
  		gfc_replace_expr (c2->as->upper[i], e);
  	      else
  		gfc_free_expr (e);
  	    }
  
! 	  c2->attr.pdt_array = 1;
  	  if (c1->initializer)
  	    {
  	      c2->initializer = gfc_copy_expr (c1->initializer);
--- 4495,4513 ----
  		gfc_replace_expr (c2->as->lower[i], e);
  	      else
  		gfc_free_expr (e);
+ 	      if (c2->as->lower[i]->expr_type != EXPR_CONSTANT)
+ 		all_constant = false;
  	      e = gfc_copy_expr (c1->as->upper[i]);
  	      gfc_insert_kind_parameter_exprs (e);
  	      if (gfc_simplify_expr (e, 1))
  		gfc_replace_expr (c2->as->upper[i], e);
  	      else
  		gfc_free_expr (e);
+ 	      if (c2->as->upper[i]->expr_type != EXPR_CONSTANT)
+ 		all_constant = false;
  	    }
  
! 	  c2->attr.pdt_array = all_constant ? 0 : 1;
  	  if (c1->initializer)
  	    {
  	      c2->initializer = gfc_copy_expr (c1->initializer);
*************** gfc_get_pdt_instance (gfc_actual_arglist
*** 4523,4529 ****
  	    gfc_replace_expr (c2->ts.u.cl->length, e);
  	  else
  	    gfc_free_expr (e);
! 	  c2->attr.pdt_string = 1;
  	}
  
        /* Recurse into this function for PDT components.  */
--- 4528,4535 ----
  	    gfc_replace_expr (c2->ts.u.cl->length, e);
  	  else
  	    gfc_free_expr (e);
! 	  if (c2->ts.u.cl->length->expr_type != EXPR_CONSTANT)
! 	    c2->attr.pdt_string = 1;
  	}
  
        /* Recurse into this function for PDT components.  */
diff -Nrcpad gcc-16-20260606/gcc/fortran/trans-intrinsic.cc gcc-16-20260613/gcc/fortran/trans-intrinsic.cc
*** gcc-16-20260606/gcc/fortran/trans-intrinsic.cc	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/fortran/trans-intrinsic.cc	Sat Jun 13 22:32:07 2026
*************** gfc_conv_intrinsic_loc (gfc_se * se, gfc
*** 9828,9836 ****
  	gfc_add_data_component (arg_expr);
        gfc_conv_expr_reference (se, arg_expr);
      }
!   else
      gfc_conv_array_parameter (se, arg_expr, true, NULL, NULL, NULL);
    se->expr = convert (gfc_get_int_type (gfc_index_integer_kind), se->expr);
  
    /* Create a temporary variable for loc return value.  Without this,
       we get an error an ICE in gcc/expr.cc(expand_expr_addr_expr_1).  */
--- 9828,9842 ----
  	gfc_add_data_component (arg_expr);
        gfc_conv_expr_reference (se, arg_expr);
      }
!   else if (gfc_is_simply_contiguous (arg_expr, false, false))
      gfc_conv_array_parameter (se, arg_expr, true, NULL, NULL, NULL);
+   else
+     {
+       gfc_conv_expr_descriptor (se, arg_expr);
+       se->expr = gfc_conv_descriptor_data_get (se->expr);
+     }
    se->expr = convert (gfc_get_int_type (gfc_index_integer_kind), se->expr);
+   se->expr = gfc_evaluate_now (se->expr, &se->pre);
  
    /* Create a temporary variable for loc return value.  Without this,
       we get an error an ICE in gcc/expr.cc(expand_expr_addr_expr_1).  */
diff -Nrcpad gcc-16-20260606/gcc/testsuite/ChangeLog gcc-16-20260613/gcc/testsuite/ChangeLog
*** gcc-16-20260606/gcc/testsuite/ChangeLog	Sat Jun  6 22:32:06 2026
--- gcc-16-20260613/gcc/testsuite/ChangeLog	Sat Jun 13 22:32:07 2026
***************
*** 1,3 ****
--- 1,103 ----
+ 2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* gcc.target/avr/torture/fx-to-double.c: New test.
+ 
+ 2026-06-11  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* lib/target-supports.exp (arm_mixed_fp): Simplify
+ 	implementation.
+ 
+ 2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-21  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/125284
+ 	PR c++/125333
+ 	* g++.dg/cpp1z/using-variadic4.C: New test.
+ 	* g++.dg/cpp1z/using-variadic5.C: New test.
+ 
+ 2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-10  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/125498
+ 	* g++.dg/reflect/mangle7.C: New test.
+ 	* g++.dg/reflect/parameters_of9.C: New test.
+ 
+ 2026-06-09  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/bigint1.adb: New  test.
+ 
+ 2026-06-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/125669
+ 	* gfortran.dg/pdt_92.f03: New test.
+ 
+ 2026-06-09  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-04-29  Xin Liu  <liulxx@hygon.cn>
+ 		    Zhaoling Bao  <baozhaoling@hygon.cn>
+ 
+ 	* gcc.target/i386/builtin_target.c: Add handling for HYGON CPUs by
+ 	validating the vendor and invoking HYGON-specific CPU detection.
+ 	* gcc.target/i386/funcspec-56.inc: Test function target attribute on
+ 	{arch,tune}=c86-4g-m{4,6,7}.
+ 	* g++.target/i386/mv33.C: New test.
+ 
+ 2026-06-08  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2026-06-06  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/125606
+ 	* gfortran.dg/loc_3.f90: New test.
+ 
+ 2026-06-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	Backported from master:
+ 	2026-06-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* g++.dg/modules/test-p1689.py: Make arrays have predictable
+ 	order.
+ 
+ 2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125611
+ 	* gcc.target/i386/ssse3-pr125611.c: New test.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-03  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/125378
+ 	* g++.dg/lookup/operator-8b.C: New test.
+ 	* g++.dg/lookup/operator-8c.C: New test.
+ 	* g++.dg/lookup/operator-9a.C: New test.
+ 	* g++.dg/lookup/operator-9b.C: New test.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-03  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	PR c++/125490
+ 	* g++.dg/cpp2a/concepts-pr125490.C: New test.
+ 	* g++.dg/cpp2a/concepts-pr125490a.C: New test.
+ 
  2026-06-03  Richard Sandiford  <rdsandiford@googlemail.com>
  
  	* gcc.dg/pr125375.c: New test.
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.dg/cpp1z/using-variadic4.C gcc-16-20260613/gcc/testsuite/g++.dg/cpp1z/using-variadic4.C
*** gcc-16-20260606/gcc/testsuite/g++.dg/cpp1z/using-variadic4.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/g++.dg/cpp1z/using-variadic4.C	Sat Jun 13 22:32:08 2026
***************
*** 0 ****
--- 1,16 ----
+ // PR c++/125284
+ // { dg-do compile { target c++17 } }
+ 
+ template<typename T>
+ struct foo {
+     operator T();
+     operator T*();
+ };
+ 
+ template<typename... T>
+ struct bar : foo<T>... {
+     using foo<T>::operator T...;
+     using foo<T>::operator T*...;
+ };
+ 
+ bar<int> z;
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.dg/cpp1z/using-variadic5.C gcc-16-20260613/gcc/testsuite/g++.dg/cpp1z/using-variadic5.C
*** gcc-16-20260606/gcc/testsuite/g++.dg/cpp1z/using-variadic5.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/g++.dg/cpp1z/using-variadic5.C	Sat Jun 13 22:32:08 2026
***************
*** 0 ****
--- 1,19 ----
+ // PR c++/125333
+ // { dg-do compile { target c++17 } }
+ 
+ template<typename... T>
+ struct X {};
+ 
+ template <typename U>
+ struct Y {
+     operator U();
+ };
+ 
+ template <typename... V>
+ struct Z : Y<V>... {
+     using Y<V>::operator V...;
+ 
+     X<V...> x;
+ };
+ 
+ Z<int, double> z;
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.dg/modules/test-p1689.py gcc-16-20260613/gcc/testsuite/g++.dg/modules/test-p1689.py
*** gcc-16-20260606/gcc/testsuite/g++.dg/modules/test-p1689.py	Sat Jun  6 22:32:08 2026
--- gcc-16-20260613/gcc/testsuite/g++.dg/modules/test-p1689.py	Sat Jun 13 22:32:09 2026
*************** def _inspect_ordering(arr):
*** 131,136 ****
--- 131,146 ----
  
      return arr, req_ordering
  
+ def _get_predictable_ordered_array(arr):
+     if not arr:
+         return arr
+ 
+     # Convert to list of string to get predictable order.
+     # Using set() here causes issue with complex arrays
+     arr = [json.dumps(x) for x in arr]
+     arr.sort()
+     return [json.loads(x) for x in arr]
+ 
  
  def compare_json(path, actual, expect):
      actual_type = type(actual)
*************** def compare_json(path, actual, expect):
*** 146,153 ****
      elif actual_type == list:
          expect, req_ordering = _inspect_ordering(expect)
          if not req_ordering:
!             actual = set(actual)
!             expect = set(expect)
          is_ok = _compare_array(path, actual, expect)
      elif actual_type == str:
          is_ok = _compare_string(path, actual, expect)
--- 156,163 ----
      elif actual_type == list:
          expect, req_ordering = _inspect_ordering(expect)
          if not req_ordering:
!             actual = _get_predictable_ordered_array(actual)
!             expect = _get_predictable_ordered_array(expect)
          is_ok = _compare_array(path, actual, expect)
      elif actual_type == str:
          is_ok = _compare_string(path, actual, expect)
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.dg/reflect/mangle7.C gcc-16-20260613/gcc/testsuite/g++.dg/reflect/mangle7.C
*** gcc-16-20260606/gcc/testsuite/g++.dg/reflect/mangle7.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/g++.dg/reflect/mangle7.C	Sat Jun 13 22:32:09 2026
***************
*** 0 ****
--- 1,65 ----
+ // PR c++/125498
+ // { dg-do compile { target c++26 } }
+ // { dg-additional-options "-freflection" }
+ 
+ #include <meta>
+ 
+ using namespace std::meta;
+ 
+ template<info>
+ void
+ xyzzy ()
+ {
+ }
+ 
+ struct S {
+   void fn1 (const S &)
+   {
+     xyzzy<parameters_of (^^S::fn1)[0]> ();
+   }
+   void fn2 (this S)
+   {
+     xyzzy<parameters_of (^^S::fn2)[0]> ();
+   }
+   static void fn3 (int)
+   {
+     xyzzy<parameters_of (^^S::fn3)[0]> ();
+   }
+ };
+ 
+ struct V : virtual S {
+   void fn1 (const V &)
+   {
+     xyzzy<parameters_of (^^V::fn1)[0]> ();
+   }
+   void fn2 (this V)
+   {
+     xyzzy<parameters_of (^^V::fn2)[0]> ();
+   }
+   static void fn3 (int)
+   {
+     xyzzy<parameters_of (^^V::fn3)[0]> ();
+   }
+ };
+ 
+ void
+ g (int)
+ {
+   xyzzy<parameters_of (^^g)[0]> ();
+   S s;
+   s.fn1 (s);
+   s.fn2 ();
+   S::fn3 (42);
+   V v;
+   v.fn1 (v);
+   v.fn2 ();
+   V::fn3 (42);
+ }
+ 
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_N1S3fn1ERKS0_EEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_NH1S3fn2ES0_EEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_N1S3fn3EiEEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_N1V3fn1ERKS0_EEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_NH1V3fn2ES0_EEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_N1V3fn3EiEEvv" } }
+ // { dg-final { scan-assembler "_Z5xyzzyILDmpa_1giEEvv" } }
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.dg/reflect/parameters_of9.C gcc-16-20260613/gcc/testsuite/g++.dg/reflect/parameters_of9.C
*** gcc-16-20260606/gcc/testsuite/g++.dg/reflect/parameters_of9.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/g++.dg/reflect/parameters_of9.C	Sat Jun 13 22:32:09 2026
***************
*** 0 ****
--- 1,45 ----
+ // PR c++/125498
+ // { dg-do compile { target c++26 } }
+ // { dg-additional-options "-freflection -g" }
+ 
+ #include <meta>
+ 
+ struct tag {};
+ 
+ struct S {
+   S(int) {}
+ };
+ 
+ struct B { };
+ struct A : virtual B { A(int); };
+ 
+ template <auto Param> struct GetAnnotations {
+   static constexpr auto value = std::define_static_array(
+       std::meta::annotations_of_with_type(Param, ^^tag));
+ };
+ 
+ consteval bool test() {
+   template for (constexpr auto member :
+ 		std::define_static_array(std::meta::members_of(
+ 		    ^^S, std::meta::access_context::unchecked()))) {
+     if constexpr (std::meta::is_constructor(member)) {
+       constexpr auto parameters =
+ 	  std::define_static_array(std::meta::parameters_of(member));
+       constexpr auto annotations = GetAnnotations<parameters[0]>::value;
+       return annotations.empty();
+     }
+   }
+ }
+ 
+ consteval bool test2() {
+   template for (constexpr auto member :
+ 		std::define_static_array(std::meta::members_of(
+ 		    ^^A, std::meta::access_context::unchecked()))) {
+     if constexpr (std::meta::is_constructor(member)) {
+       constexpr auto parameters =
+ 	  std::define_static_array(std::meta::parameters_of(member));
+       constexpr auto annotations = GetAnnotations<parameters[0]>::value;
+       return annotations.empty();
+     }
+   }
+ }
diff -Nrcpad gcc-16-20260606/gcc/testsuite/g++.target/i386/mv33.C gcc-16-20260613/gcc/testsuite/g++.target/i386/mv33.C
*** gcc-16-20260606/gcc/testsuite/g++.target/i386/mv33.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/g++.target/i386/mv33.C	Sat Jun 13 22:32:09 2026
***************
*** 0 ****
--- 1,42 ----
+ // Test that dispatching can choose the right multiversion
+ // for HYGON CPUs with the same internal GCC processor id
+ 
+ // { dg-do run }
+ // { dg-require-ifunc "" }
+ // { dg-options "-O2" }
+ 
+ #include <assert.h>
+ 
+ int __attribute__ ((target("default")))
+ foo ()
+ {
+   return 0;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m4"))) foo () {
+   return 1;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m6"))) foo () {
+   return 2;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m7"))) foo () {
+   return 3;
+ }
+ 
+ int main ()
+ {
+   int val = foo ();
+ 
+   if  (__builtin_cpu_is ("c86-4g-m4"))
+     assert (val == 1);
+   else if (__builtin_cpu_is ("c86-4g-m6"))
+     assert (val == 2);
+   else if (__builtin_cpu_is ("c86-4g-m7"))
+     assert (val == 3);
+   else
+     assert (val == 0);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.dg/Wreturn-nested-3.c gcc-16-20260613/gcc/testsuite/gcc.dg/Wreturn-nested-3.c
*** gcc-16-20260606/gcc/testsuite/gcc.dg/Wreturn-nested-3.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gcc.dg/Wreturn-nested-3.c	Sat Jun 13 22:32:10 2026
***************
*** 0 ****
--- 1,42 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target trampolines } */
+ /* { dg-options "" } */
+ 
+ 
+ void *a0() {
+   int b = 1;
+   struct bar { char c[b]; };
+   struct bar e() { struct bar f; return f; }
+   return &e;	/* { dg-warning "referencing local context" } */
+ }
+ 
+ void *a1() {
+   int b = 1;
+   struct bar { char c[b]; };
+   struct bar e() { }
+   return &e;
+ }
+ 
+ void *a2() {
+   int b = 1;
+   struct bar { char c[b]; };
+   struct bar e() { typeof(struct bar) f; return f; }
+   return &e;	/* { dg-warning "referencing local context" } */
+ }
+ 
+ void *a3() {
+   int b = 1;
+   struct bar { char c[b]; };
+   struct bar (*d)();
+   struct bar e() { typeof((*d)()) f; return f; }
+   return &e;	/* { dg-warning "referencing local context" } */
+ }
+ 
+ void *a4() {
+   int b = 1;
+   struct bar { char c[b]; };
+   struct bar e() { struct bar f; return f; }
+   return &e;	/* { dg-warning "referencing local context" } */
+ }
+ 
+ 
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.dg/pr124303.c gcc-16-20260613/gcc/testsuite/gcc.dg/pr124303.c
*** gcc-16-20260606/gcc/testsuite/gcc.dg/pr124303.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gcc.dg/pr124303.c	Sat Jun 13 22:32:10 2026
***************
*** 0 ****
--- 1,7 ----
+ /* { dg-do compile } */
+ /* { dg-options "-std=c23" } */
+ 
+ struct s { void (*p)(const struct s*); };
+ struct s { void (*p)(const struct s*); };
+ 
+ 
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.dg/pr124985.c gcc-16-20260613/gcc/testsuite/gcc.dg/pr124985.c
*** gcc-16-20260606/gcc/testsuite/gcc.dg/pr124985.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gcc.dg/pr124985.c	Sat Jun 13 22:32:10 2026
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target trampolines } */
+ /* { dg-options "-O1 -fno-tree-dse" } */
+ 
+ void a() {
+   int b = 0;
+   struct bar { char c[b]; };
+   struct bar (*d)();
+   struct bar e() { struct bar f; return f; }
+   d = e;
+   d();
+ }
+ 
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.dg/pr125252.c gcc-16-20260613/gcc/testsuite/gcc.dg/pr125252.c
*** gcc-16-20260606/gcc/testsuite/gcc.dg/pr125252.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gcc.dg/pr125252.c	Sat Jun 13 22:32:10 2026
***************
*** 0 ****
--- 1,36 ----
+ /* { dg-do run } */
+ /* { dg-options "-std=gnu23 -O2" } */
+ 
+ 
+ int k;
+ struct S {};
+ 
+ #define T struct S
+ 
+ T *get_sender () {
+   k = 1;
+   return (void *)0;
+ }
+ 
+ T *get_cc () { }
+ 
+ void test () {
+         struct {
+                 T *(*get_header) (void);
+         } reply_to_map[] = {
+                 { get_sender },
+                 { get_cc },
+         };
+ 
+         for (int i = 0; i < 2; i++) {
+                 asm ("" ::"r"(reply_to_map[i].get_header ()));
+         }
+ }
+ 
+ int main() {
+         test ();
+ 
+         if (k != 1)
+             __builtin_abort();
+ }
+ 
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.target/avr/torture/fx-to-double.c gcc-16-20260613/gcc/testsuite/gcc.target/avr/torture/fx-to-double.c
*** gcc-16-20260606/gcc/testsuite/gcc.target/avr/torture/fx-to-double.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gcc.target/avr/torture/fx-to-double.c	Sat Jun 13 22:32:11 2026
***************
*** 0 ****
--- 1,88 ----
+ /* { dg-do run { target { ! avr_tiny } } } */
+ /* { dg-additional-options "-std=gnu99 -Wno-pedantic" } */
+ 
+ typedef long double DD;
+ 
+ typedef long long _Fract dq_t;
+ typedef long long _Accum ta_t;
+ typedef long _Accum da_t;
+ typedef unsigned long long _Fract udq_t;
+ typedef unsigned long long _Accum uta_t;
+ typedef unsigned long _Accum uda_t;
+ 
+ #define NI __attribute__((noipa))
+ 
+ #define MK_CONV(T)				\
+   NI DD T##2d (T##_t x)				\
+   {						\
+     __asm ("" : "+r" (x));			\
+     return (DD) x;				\
+   }						\
+ 						\
+   NI T##_t d2##T (DD x)				\
+   {						\
+     __asm ("" : "+r" (x));			\
+     return (T##_t) x;				\
+   }
+ 
+ 
+ MK_CONV (da)
+ MK_CONV (ta)
+ MK_CONV (dq)
+ 
+ MK_CONV (uda)
+ MK_CONV (uta)
+ MK_CONV (udq)
+ 
+ #define TEST(T)					\
+   do {						\
+     T##_t fx = d2##T (x);			\
+     DD y = T##2d (fx);				\
+     if (y != x)					\
+       __builtin_exit (__LINE__);		\
+   } while (0)
+ 
+ 
+ NI void test_s (DD x)
+ {
+   TEST (da);
+   TEST (ta);
+ 
+   if (x < 1.0L && x >= -1.0L)
+     TEST (dq);
+ }
+ 
+ 
+ NI void test_u (long double x)
+ {
+   TEST (uda);
+   TEST (uta);
+ 
+   if (x < 1.0L)
+     TEST (udq);
+ }
+ 
+ void test (DD x)
+ {
+   if (x >= 0)
+     test_u (x);
+ 
+   test_s (x);
+ }
+ 
+ int main (void)
+ {
+   test (+0.0L);
+   test (-0.0L);
+ 
+   test (+1.0L);
+   test (-1.0L);
+ 
+   test (-0x0.cafe123p0);
+   test (+0x0.cafe123p0);
+ 
+   test (+0x1234.cafe123p0);
+   test (-0x1234.cafe123p0);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.target/i386/builtin_target.c gcc-16-20260613/gcc/testsuite/gcc.target/i386/builtin_target.c
*** gcc-16-20260606/gcc/testsuite/gcc.target/i386/builtin_target.c	Sat Jun  6 22:32:11 2026
--- gcc-16-20260613/gcc/testsuite/gcc.target/i386/builtin_target.c	Sat Jun 13 22:32:11 2026
*************** check_detailed ()
*** 54,59 ****
--- 54,63 ----
        assert (__builtin_cpu_is ("amd"));
        get_amd_cpu (&cpu_model, &cpu_model2, cpu_features2);
        break;
+     case VENDOR_HYGON:
+       assert (__builtin_cpu_is ("hygon"));
+       get_hygon_cpu (&cpu_model, &cpu_model2, cpu_features2);
+       break;
      default:
        break;
      }
*************** quick_check ()
*** 127,132 ****
--- 131,138 ----
  
    assert (__builtin_cpu_is ("bdver2") >= 0);
  
+   assert (__builtin_cpu_is ("c86-4g-m4") >= 0);
+ 
    return 0;
  }
  
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gcc.target/i386/funcspec-56.inc gcc-16-20260613/gcc/testsuite/gcc.target/i386/funcspec-56.inc
*** gcc-16-20260606/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Sat Jun  6 22:32:11 2026
--- gcc-16-20260613/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Sat Jun 13 22:32:12 2026
*************** extern void test_arch_znver3 (void)
*** 239,244 ****
--- 239,247 ----
  extern void test_arch_znver4 (void)             __attribute__((__target__("arch=znver4")));
  extern void test_arch_znver5 (void)             __attribute__((__target__("arch=znver5")));
  extern void test_arch_znver6 (void)             __attribute__((__target__("arch=znver6")));
+ extern void test_arch_c86_4g_m4 (void)          __attribute__((__target__("arch=c86-4g-m4")));
+ extern void test_arch_c86_4g_m6 (void)          __attribute__((__target__("arch=c86-4g-m6")));
+ extern void test_arch_c86_4g_m7 (void)          __attribute__((__target__("arch=c86-4g-m7")));
  
  extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
  extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
*************** extern void test_tune_znver3 (void)
*** 267,272 ****
--- 270,278 ----
  extern void test_tune_znver4 (void)             __attribute__((__target__("tune=znver4")));
  extern void test_tune_znver5 (void)             __attribute__((__target__("tune=znver5")));
  extern void test_tune_znver6 (void)             __attribute__((__target__("tune=znver6")));
+ extern void test_tune_c86_4g_m4 (void)          __attribute__((__target__("tune=c86-4g-m4")));
+ extern void test_tune_c86_4g_m6 (void)          __attribute__((__target__("tune=c86-4g-m6")));
+ extern void test_tune_c86_4g_m7 (void)          __attribute__((__target__("tune=c86-4g-m7")));
  
  extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
  extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gfortran.dg/loc_3.f90 gcc-16-20260613/gcc/testsuite/gfortran.dg/loc_3.f90
*** gcc-16-20260606/gcc/testsuite/gfortran.dg/loc_3.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gfortran.dg/loc_3.f90	Sat Jun 13 22:32:13 2026
***************
*** 0 ****
--- 1,36 ----
+ ! { dg-do compile }
+ ! { dg-additional-options "-O1" }
+ !
+ ! PR fortran/125606
+ !
+ ! Derived from Fujitsu testsuite
+ ! Reported by David Binderman
+ 
+ module m
+   implicit none
+   type ty
+      class(*), allocatable :: c1(:)
+   end type ty
+   type tt
+      class(*), allocatable :: node1(:)
+   end type tt
+   type,extends(tt)::tte
+      class(*), allocatable :: c2e(:)
+   end type tte
+ contains
+   subroutine put_addr
+     class(*), allocatable :: t(:)
+     integer :: unit
+     select type (t)
+     class is (tt)
+        select type (p=>t(2)%node1)
+        class is (ty)
+           write (unit) loc(p(2)%c1)
+        end select
+        select type (t)
+        type is (tte)
+           write (7) loc(t(2)%c2e)
+        end select
+     end select
+   end subroutine put_addr
+ end module m
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gfortran.dg/pdt_92.f03 gcc-16-20260613/gcc/testsuite/gfortran.dg/pdt_92.f03
*** gcc-16-20260606/gcc/testsuite/gfortran.dg/pdt_92.f03	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gfortran.dg/pdt_92.f03	Sat Jun 13 22:32:13 2026
***************
*** 0 ****
--- 1,25 ----
+ ! { dg-do compile }
+ ! { dg-options "-fdump-tree-original" }
+ !
+ ! Test the fix for pr125669, in which the components 'v' and 'c' below were
+ ! allocated and freed unnecessarily.
+ !
+ module m
+   implicit none
+   type :: t(k1, k2)
+     integer, kind :: k1, k2
+     real :: v(k1*k2, max(k1,k2))
+     character(len = k1+k2-1) :: c
+   end type
+ end module
+ 
+ program p
+   use m
+   implicit none
+   integer, parameter :: n=3, k=2
+   type(t(n,k)) :: x
+   if (any (shape(x%v) /= [6,3])) stop 1
+   if (len(x%c) /= 4) stop 2
+ end program
+ ! { dg-final { scan-tree-dump-times "__builtin_malloc" 0 "original" } }
+ ! { dg-final { scan-tree-dump-times "__builtin_free" 0 "original" } }
diff -Nrcpad gcc-16-20260606/gcc/testsuite/gnat.dg/bigint1.adb gcc-16-20260613/gcc/testsuite/gnat.dg/bigint1.adb
*** gcc-16-20260606/gcc/testsuite/gnat.dg/bigint1.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20260613/gcc/testsuite/gnat.dg/bigint1.adb	Sat Jun 13 22:32:13 2026
***************
*** 0 ****
--- 1,27 ----
+ -- { dg-do run }
+ -- { dg-options "-gnat2022 -gnata" }
+ 
+ with Ada.Numerics.Big_Numbers.Big_Integers;
+ use Ada.Numerics.Big_Numbers.Big_Integers;
+ 
+ procedure Bigint1 is
+ 
+   Minus_One   : constant Big_Integer := To_Big_Integer (-1);
+   Minus_Two   : constant Big_Integer := To_Big_Integer (-2);
+   Minus_Three : constant Big_Integer := To_Big_Integer (-3);
+ 
+ begin
+ 
+   pragma Assert (Minus_One ** 1 = Minus_One);
+   pragma Assert (Minus_One ** 2 = To_Big_Integer (1));
+   pragma Assert (Minus_One ** 3 = Minus_One);
+ 
+   pragma Assert (Minus_Two ** 1 = Minus_Two);
+   pragma Assert (Minus_Two ** 2 = To_Big_Integer (4));
+   pragma Assert (Minus_Two ** 3 = To_Big_Integer (-8));
+ 
+   pragma Assert (Minus_Three ** 1 = Minus_Three);
+   pragma Assert (Minus_Three ** 2 = To_Big_Integer (9));
+   pragma Assert (Minus_Three ** 3 = To_Big_Integer (-27));
+ 
+ end;
diff -Nrcpad gcc-16-20260606/gcc/testsuite/lib/target-supports.exp gcc-16-20260613/gcc/testsuite/lib/target-supports.exp
*** gcc-16-20260606/gcc/testsuite/lib/target-supports.exp	Sat Jun  6 22:32:14 2026
--- gcc-16-20260613/gcc/testsuite/lib/target-supports.exp	Sat Jun 13 22:32:14 2026
*************** proc check_effective_target_arm_mixed_fp
*** 6383,6392 ****
      }
  
      return [check_no_compiler_messages arm_mixed_fp assembly {
! 	#ifndef __ARM_FP
! 	# error __ARM_FP not defined
! 	#elif ((__ARM_FP & 0xc) == 0xc)
! 	# error __ARM_FP indicates that both single- and double-precision FP are supported
  	#endif
  	int main (void) { return 0; }
      } "" ]
--- 6383,6391 ----
      }
  
      return [check_no_compiler_messages arm_mixed_fp assembly {
! 	// Mixed FP means we have hw FP, but only for SFmode (ignores HFmode)
! 	#if !defined(__ARM_FP) || ((__ARM_FP & 0xc) != 0x4)
! 	#error Not mixed FP
  	#endif
  	int main (void) { return 0; }
      } "" ]
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/ChangeLog gcc-16-20260613/libgcc/config/avr/libf7/ChangeLog
*** gcc-16-20260606/libgcc/config/avr/libf7/ChangeLog	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/ChangeLog	Sat Jun 13 22:32:14 2026
***************
*** 1,3 ****
--- 1,22 ----
+ 2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* libf7-asm.sx (ufx64_to_d, d_to_fx64): New DEFUNs.
+ 	(__fractdadf, __fractudadf, __fracttadf, __fractutadf)
+ 	(__fractdqdf, __fractudqdf): New _DEFUNs.
+ 	* libf7-common.mk (F7_ASM_PARTS) Add: fx2D, D2fx,
+ 	dq2D, udq2D, da2D, uda2D, ta2D uta2D.
+ 	(F7F): Add d_to_fx64, ufx64_to_d, sfx64_to_d.
+ 	* libf7.c (d_to_ufx, d_to_sfx): New protos.
+ 	(__fractdfda, __fractdfuda, __fractdfta, __fractdfuta)
+ 	(__fractdfdq, __fractdfudq): New modules.
+ 	* t-libf7 (LIBF7_DF_CONV): Add fractdfda,
+ 	fractdfta, fractdfdq, fractdfuda, fractdfuta, fractdfudq.
+ 	* f7-renames.h: Rebuild.
+ 
  2026-04-30  Release Manager
  
  	* GCC 16.1.0 released.
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/f7-renames.h gcc-16-20260613/libgcc/config/avr/libf7/f7-renames.h
*** gcc-16-20260606/libgcc/config/avr/libf7/f7-renames.h	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/f7-renames.h	Sat Jun 13 22:32:14 2026
***************
*** 222,227 ****
--- 222,230 ----
  #define f7_sqrt16_floor_asm __f7_sqrt16_floor_asm
  #define f7_lshrdi3_asm __f7_lshrdi3_asm
  #define f7_ashldi3_asm __f7_ashldi3_asm
+ #define f7_d_to_fx64_asm __f7_d_to_fx64_asm
+ #define f7_ufx64_to_d_asm __f7_ufx64_to_d_asm
+ #define f7_sfx64_to_d_asm __f7_sfx64_to_d_asm
  #define f7_class_D_asm __f7_class_D_asm
  #define f7_call_ddd_asm __f7_call_ddd_asm
  #define f7_call_xdd_asm __f7_call_xdd_asm
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/libf7-asm.sx gcc-16-20260613/libgcc/config/avr/libf7/libf7-asm.sx
*** gcc-16-20260606/libgcc/config/avr/libf7/libf7-asm.sx	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/libf7-asm.sx	Sat Jun 13 22:32:14 2026
*************** _ENDF __fractqqdf
*** 2308,2315 ****
  #endif /* F7MOD_qq2D_ */
  
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
! ;;; Fixed-point -> double conversions.
  
  #ifdef F7MOD_D2qq_
  _DEFUN __fractdfqq
--- 2308,2392 ----
  #endif /* F7MOD_qq2D_ */
  
  
+ #ifdef F7MOD_fx2D_
+ ;;; Convert an [un]signed 64-bit fixed point value R18[] to double.
+ ;;;    double ufx64_to_d (ufx64_t R18, uint8_t fbit R30);
+ ;;;    double sfx64_to_d (sfx64_t R18, uint8_t fbit R30);
+ ;;; FBIT accounts for the fractional bits of the fixed point type,
+ ;;; e.g. pass __DA_FBIT__ for long accum etc.
+ DEFUN ufx64_to_d
+     push    r30
+     XCALL __floatundidf
+     rjmp  1f
+ 
+ LABEL sfx64_to_d
+     push    r30
+     XCALL __floatdidf
+ 1:  pop     r30
+ 
+     ;; The MSB indicates a value of 0.  Notice that at this point,
+     ;; we have a normal floating point number with a biased exponent
+     ;; that won't underflow below.
+     tst     r25
+     breq 0f
+ 
+     ;; Subtract fbit from the double exponent.  R30[] = fbit << 4.
+     swap    r30
+     mov     r31, r30
+     andi    r30, lo8 (0x0ff0)
+     andi    r31, hi8 (0x0ff0)
+     sub     r24, r30
+     sbc     r25, r31
+ 
+ 0:  ret
+ ENDF ufx64_to_d
+ #endif /* F7MOD_fx2D_ */
+ 
+ #ifdef F7MOD_da2D_
+ _DEFUN __fractdadf
+     ldi     r30, __DA_FBIT__
+     F7jmp   sfx64_to_d
+ _ENDF __fractdadf
+ #endif /* F7MOD_da2D_ */
+ 
+ #ifdef F7MOD_uda2D_
+ _DEFUN __fractudadf
+     ldi     r30, __UDA_FBIT__
+     F7jmp   ufx64_to_d
+ _ENDF __fractudadf
+ #endif /* F7MOD_uda2D_ */
+ 
+ #ifdef F7MOD_ta2D_
+ _DEFUN __fracttadf
+     ldi     r30, __TA_FBIT__
+     F7jmp   sfx64_to_d
+ _ENDF __fracttadf
+ #endif /* F7MOD_ta2D_ */
+ 
+ #ifdef F7MOD_uta2D_
+ _DEFUN __fractutadf
+     ldi     r30, __UTA_FBIT__
+     F7jmp   ufx64_to_d
+ _ENDF __fractutadf
+ #endif /* F7MOD_uta2D_ */
+ 
+ #ifdef F7MOD_dq2D_
+ _DEFUN __fractdqdf
+     ldi     r30, __DQ_FBIT__
+     F7jmp   sfx64_to_d
+ _ENDF __fractdqdf
+ #endif /* F7MOD_dq2D_ */
+ 
+ #ifdef F7MOD_udq2D_
+ _DEFUN __fractudqdf
+     ldi     r30, __UDQ_FBIT__
+     F7jmp   ufx64_to_d
+ _ENDF __fractudqdf
+ #endif /* F7MOD_udq2D_ */
+ 
+ 
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
! ;;; Double -> fixed-point conversions.
  
  #ifdef F7MOD_D2qq_
  _DEFUN __fractdfqq
*************** _ENDF __fractdfusa
*** 2389,2394 ****
--- 2466,2514 ----
  #endif /* F7MOD_D2usa_ */
  
  
+ #ifdef F7MOD_D2fx_
+ ;;; Convert double R18 to a 64-bit fixed point value.
+ ;;; R18 d_to_fx64 (double R18, int8_t fbit R16);
+ ;;; |FBIT| accounts for the extra fbits compared to [u]int64_t.
+ ;;; FBIT < 0 indicates a signed conversion.
+ ;;; FBIT > 0 indicates an unsigned conversion.
+ DEFUN d_to_fx64
+     do_prologue_saves  4, F7_SIZEOF
+ 
+     ;; Y = FramePointer + 1
+     adiw    Y,      1
+ 
+     ;; FP + 1 = (f7_t) arg
+     wmov    r16,    Y
+ 
+     ;; Convert double R18 to f7_t *R16.
+     XCALL   F7_NAME (set_double_impl)
+ 
+     ;; Prepare for *R24 = ldexp (*R24, R22).  ldexp() accounts for the
+     ;; fractional bits of the fixed point value, i.e. we have to <<= FBIT.
+     wmov    r24,    r16
+     ;; Zero-extend FBIT.
+     clr     r23
+     ;; R16 has been clobbered.  Fetch it from where prologue_saves put it.
+     ldd     r22,    Y + F7_SIZEOF + 3       ; Saved R16
+     tst     r22
+     brmi 1f
+ 
+     ;; Positive FBIT indicates an unsigned conversion.
+     XCALL   F7_NAME (Ildexp)
+     XCALL   F7_NAME (get_u64)
+     rjmp 9f
+ 
+ 1:  ;; Negative FBIT indicates a signed conversion.
+     neg     r22                 ; FBIT := |FBIT|
+     XCALL   F7_NAME (Ildexp)
+     XCALL   F7_NAME (get_s64)
+ 
+ 9:  do_epilogue_restores  4, F7_SIZEOF
+ ENDF d_to_fx64
+ #endif /* F7MOD_D2fx_ */
+ 
+ 
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  ;;; [u]int32_t -> double conversions.
  
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/libf7-common.mk gcc-16-20260613/libgcc/config/avr/libf7/libf7-common.mk
*** gcc-16-20260606/libgcc/config/avr/libf7/libf7-common.mk	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/libf7-common.mk	Sat Jun 13 22:32:14 2026
*************** F7_ASM_PARTS += D_cmp D_eq D_ne D_ge D_g
*** 29,40 ****
  F7_ASM_PARTS += call_dd call_ddd
  
  # Fixed-point -> double conversions
! F7_ASM_PARTS += qq2D uqq2D            sq2D usq2D
! F7_ASM_PARTS +=            ha2D uha2D sa2D usa2D
  
  # Double -> fixed-point conversions
  F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq
  F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
--- 29,42 ----
  F7_ASM_PARTS += call_dd call_ddd
  
  # Fixed-point -> double conversions
! F7_ASM_PARTS += qq2D uqq2D            sq2D usq2D dq2D udq2D
! F7_ASM_PARTS +=            ha2D uha2D sa2D usa2D da2D uda2D ta2D uta2D
! F7_ASM_PARTS += fx2D
  
  # Double -> fixed-point conversions
  F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq
  F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa
+ F7_ASM_PARTS += D2fx
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
*************** F7F_asm += set_u64 set_s64 addsub_mant_s
*** 107,113 ****
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! 
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
--- 109,115 ----
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! F7F_asm += d_to_fx64 ufx64_to_d sfx64_to_d
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/libf7.c gcc-16-20260613/libgcc/config/avr/libf7/libf7.c
*** gcc-16-20260606/libgcc/config/avr/libf7/libf7.c	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/libf7.c	Sat Jun 13 22:32:14 2026
*************** f7_double_t __floatdidf (int64_t x)
*** 140,145 ****
--- 140,197 ----
  #endif // F7MOD_floatdidf_
  
  
+ extern uint64_t d_to_ufx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
+ extern int64_t  d_to_sfx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
+ 
+ #ifdef F7MOD_fractdfda_
+ F7_WEAK
+ int64_t __fractdfda (f7_double_t d)
+ {
+   return d_to_sfx (d, -__DA_FBIT__);
+ }
+ #endif // F7MOD_fractdfda_
+ 
+ #ifdef F7MOD_fractdfuda_
+ F7_WEAK
+ uint64_t __fractdfuda (f7_double_t d)
+ {
+   return d_to_ufx (d, __UDA_FBIT__);
+ }
+ #endif // F7MOD_fractdfuda_
+ 
+ #ifdef F7MOD_fractdfta_
+ F7_WEAK
+ int64_t __fractdfta (f7_double_t d)
+ {
+   return d_to_sfx (d, -__TA_FBIT__);
+ }
+ #endif // F7MOD_fractdfta_
+ 
+ #ifdef F7MOD_fractdfuta_
+ F7_WEAK
+ uint64_t __fractdfuta (f7_double_t d)
+ {
+   return d_to_ufx (d, __UTA_FBIT__);
+ }
+ #endif // F7MOD_fractdfuta_
+ 
+ #ifdef F7MOD_fractdfdq_
+ F7_WEAK
+ int64_t __fractdfdq (f7_double_t d)
+ {
+   return d_to_sfx (d, -__DQ_FBIT__);
+ }
+ #endif // F7MOD_fractdfdq_
+ 
+ #ifdef F7MOD_fractdfudq_
+ F7_WEAK
+ uint64_t __fractdfudq (f7_double_t d)
+ {
+   return d_to_ufx (d, __UDQ_FBIT__);
+ }
+ #endif // F7MOD_fractdfudq_
+ 
+ 
  #ifdef F7MOD_init_
  f7_t* f7_init_impl (uint64_t mant, uint8_t flags, f7_t *cc, int16_t expo)
  {
diff -Nrcpad gcc-16-20260606/libgcc/config/avr/libf7/t-libf7 gcc-16-20260613/libgcc/config/avr/libf7/t-libf7
*** gcc-16-20260606/libgcc/config/avr/libf7/t-libf7	Sat Jun  6 22:32:15 2026
--- gcc-16-20260613/libgcc/config/avr/libf7/t-libf7	Sat Jun 13 22:32:14 2026
*************** F7_PREFIX = __f7_
*** 9,14 ****
--- 9,16 ----
  include $(libf7)/libf7-common.mk
  
  LIBF7_DF_CONV +=  floatundidf floatdidf # floatunsidf floatsidf
+ LIBF7_DF_CONV +=  fractdfda fractdfta fractdfdq
+ LIBF7_DF_CONV +=  fractdfuda fractdfuta fractdfudq
  
  # Wrappers like f7_lt_impl for f7_lt etc. because the latter is inline.
  LIBF7_DF_CMP  += lt le gt ge ne eq unord
diff -Nrcpad gcc-16-20260606/libstdc++-v3/ChangeLog gcc-16-20260613/libstdc++-v3/ChangeLog
*** gcc-16-20260606/libstdc++-v3/ChangeLog	Sat Jun  6 22:32:17 2026
--- gcc-16-20260613/libstdc++-v3/ChangeLog	Sat Jun 13 22:32:15 2026
***************
*** 1,3 ****
--- 1,93 ----
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-29  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* include/std/flat_set (_Flat_set_impl::swap): Swap _M_cont
+ 	first.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* include/std/flat_map (flat_map): Bring in operator= from
+ 	_Flat_map_base.
+ 	(flat_multimap): Likewise.
+ 	* include/std/flat_set (flat_set): Bring in operator= from
+ 	_Flat_set_base.
+ 	(flat_multiset): Likewise.
+ 	* testsuite/23_containers/flat_map/1.cc (test11): Simplify by
+ 	using = {...}.
+ 	(test12): New test.
+ 	* testsuite/23_containers/flat_multimap/1.cc (test10): Simplify
+ 	by using = {...}.
+ 	(test11): New test.
+ 	* testsuite/23_containers/flat_multiset/1.cc (test10): Simplify
+ 	by using = {...}.
+ 	(test11): New test.
+ 	* testsuite/23_containers/flat_set/1.cc (test10): Simplify by
+ 	using = {...}.
+ 	(test11): New test.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* include/bits/version.def (flat_map): Bump to 202511.
+ 	(flat_set): Likewise.
+ 	* include/bits/version.h: Regenerate.
+ 	* include/std/flat_map (_Flat_map_impl): Remove
+ 	is_nothrow_swappable_v assertions.
+ 	(_Flat_map_impl::_Flat_map_impl): Explicitly default copy ctor.
+ 	Define move ctor with corrected exception handling as per
+ 	P3567R2.
+ 	(_Flat_map_impl::operator=): Likewise.
+ 	(_Flat_map_impl::insert_range): Define new __sorted_t overload
+ 	as per P3567R2.
+ 	(_Flat_map_impl::swap): Make conditionally noexcept as per
+ 	P3567R2.
+ 	* include/std/flat_set (_Flat_set_impl): Remove
+ 	is_nothrow_swappable_v assertion.
+ 	(_Flat_set_impl::_Flat_set_impl): Explicitly default copy ctor.
+ 	Define move ctor with correct invariant preserving behavior as
+ 	per P3567R2.
+ 	(_Flat_set_impl::operator=): Likewise.
+ 	(_Flat_set_impl::_M_insert_range): Factored out from
+ 	insert_range.  Add bool parameter __is_sorted defaulted to
+ 	false.
+ 	(_Flat_set_impl::insert_range): Define new __sorted_t overload
+ 	as per P3567R2.
+ 	(_Flat_set_impl::swap): Make conditionally noexcept as per
+ 	P3567R2.  Correct to use ranges::swap instead of ADL swap.
+ 	* testsuite/23_containers/flat_map/1.cc (test11, test12):
+ 	New tests.
+ 	* testsuite/23_containers/flat_multimap/1.cc (test10, test11):
+ 	New tests.
+ 	* testsuite/23_containers/flat_multiset/1.cc (test10, test11):
+ 	New tests.
+ 	* testsuite/23_containers/flat_set/1.cc (test10, test11):
+ 	New tests.
+ 
+ 2026-06-04  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Patrick Palka  <ppalka@redhat.com>
+ 
+ 	* include/std/flat_map (_Flat_map_impl::_M_insert): New bool
+ 	parameter __is_sorted defaulted to false.  Reimplement using
+ 	views::zip and ranges::inplace_merge.
+ 	(_Flat_map_impl::insert): In the __sorted_t overload, pass
+ 	__is_sorted=true to _M_insert.
+ 
+ 2026-06-04  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-04  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	* include/debug/safe_iterator.h: Remove trailing whitespace.
+ 
  2026-05-27  Jonathan Wakely  <jwakely@redhat.com>
  
  	Backported from master:
